/**
 @file sys_usw_mchip.h

 @date 2009-10-19

 @version v2.0

 The file contains chip independent related APIs of sys layer
*/

#ifndef _SYS_USW_MCHIP_H
#define _SYS_USW_MCHIP_H
#ifdef __cplusplus
extern "C" {
#endif

/****************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sal.h"
#include "ctc_const.h"
#include "drv_api.h"
#include "ctc_l3if.h"
#include "ctc_ipuc.h"
#include "ctc_scl.h"
#include "ctc_acl.h"
#include "ctc_packet.h"
#include "ctc_nexthop.h"
#include "ctc_flexe.h"
#include "ctc_dot1ae.h"
#include "ctc_diag.h"
#include "ctc_eunit.h"
#include "sys_usw_ftm.h"
#include "sys_usw_chip.h"
#include "sys_usw_opf.h"
#include "sys_usw_port_api.h"

enum sys_mchip_capability_e
{
    SYS_CAP_SPEC_LOGIC_PORT_NUM = 0,
    SYS_CAP_SPEC_MAX_FID,
    SYS_CAP_SPEC_MAX_VRFID,
    SYS_CAP_SPEC_MCAST_GROUP_NUM,
    SYS_CAP_SPEC_VLAN_NUM,
    SYS_CAP_SPEC_VLAN_RANGE_GROUP_NUM,
    SYS_CAP_SPEC_STP_INSTANCE_NUM,
    SYS_CAP_SPEC_LINKAGG_GROUP_NUM,
    SYS_CAP_SPEC_LINKAGG_MEMBER_NUM,
    SYS_CAP_SPEC_LINKAGG_DLB_FLOW_NUM,
    SYS_CAP_SPEC_LINKAGG_DLB_MEMBER_NUM,
    SYS_CAP_SPEC_LINKAGG_DLB_GROUP_NUM,
    SYS_CAP_SPEC_ECMP_GROUP_NUM,
    SYS_CAP_SPEC_ECMP_MEMBER_NUM,
    SYS_CAP_SPEC_ECMP_DLB_FLOW_NUM,
    SYS_CAP_SPEC_EXTERNAL_NEXTHOP_NUM,
    SYS_CAP_SPEC_GLOBAL_DSNH_NUM,
    SYS_CAP_SPEC_MPLS_TUNNEL_NUM,
    SYS_CAP_SPEC_ARP_ID_NUM,
    SYS_CAP_SPEC_L3IF_NUM,
    SYS_CAP_SPEC_OAM_SESSION_NUM,
    SYS_CAP_SPEC_NPM_SESSION_NUM,
    SYS_CAP_SPEC_TOTAL_POLICER_NUM,
    SYS_CAP_SPEC_POLICER_NUM,
    SYS_CAP_SPEC_TOTAL_STATS_NUM,
    SYS_CAP_SPEC_QUEUE_STATS_NUM,
    SYS_CAP_SPEC_POLICER_STATS_NUM,
    SYS_CAP_SPEC_SHARE1_STATS_NUM,
    SYS_CAP_SPEC_SHARE2_STATS_NUM,
    SYS_CAP_SPEC_SHARE3_STATS_NUM,
    SYS_CAP_SPEC_SHARE4_STATS_NUM,
    SYS_CAP_SPEC_SHARE5_STATS_NUM,
    SYS_CAP_SPEC_SHARE6_STATS_NUM,
    SYS_CAP_SPEC_SHARE7_STATS_NUM,
    SYS_CAP_SPEC_SHARE8_STATS_NUM,
    SYS_CAP_SPEC_SHARE9_STATS_NUM,
    SYS_CAP_SPEC_SHARE10_STATS_NUM,
    SYS_CAP_SPEC_SHARE11_STATS_NUM,
    SYS_CAP_SPEC_SHARE12_STATS_NUM,
    SYS_CAP_SPEC_SHARE13_STATS_NUM,
    SYS_CAP_SPEC_SHARE14_STATS_NUM,
    SYS_CAP_SPEC_SHARE15_STATS_NUM,
    SYS_CAP_SPEC_SHARE16_STATS_NUM,
    SYS_CAP_SPEC_ACL0_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL1_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL2_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL3_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL4_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL5_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL6_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL7_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL8_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL9_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL10_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL11_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL12_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL13_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL14_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL15_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL16_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL17_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL18_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL19_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL20_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL21_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL22_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL23_IGS_STATS_NUM,
    SYS_CAP_SPEC_ACL0_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL1_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL2_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL3_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL4_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL5_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL6_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL7_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL8_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL9_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL10_EGS_STATS_NUM,
    SYS_CAP_SPEC_ACL11_EGS_STATS_NUM,
    SYS_CAP_SPEC_ECMP_STATS_NUM,
    SYS_CAP_SPEC_ROUTE_MAC_ENTRY_NUM,
    SYS_CAP_SPEC_MAC_ENTRY_NUM,
     /*SYS_CAP_SPEC_BLACK_HOLE_ENTRY_NUM,*/
    SYS_CAP_SPEC_HOST_ROUTE_ENTRY_NUM,
    SYS_CAP_SPEC_LPM_ROUTE_ENTRY_NUM,
    SYS_CAP_SPEC_IPMC_ENTRY_NUM,
    SYS_CAP_SPEC_MPLS_ENTRY_NUM,
    SYS_CAP_SPEC_TUNNEL_ENTRY_NUM,
     /*SYS_CAP_SPEC_L2PDU_L2HDR_PROTO_ENTRY_NUM,*/
     /*SYS_CAP_SPEC_L2PDU_MACDA_ENTRY_NUM,*/
     /*SYS_CAP_SPEC_L2PDU_MACDA_LOW24_ENTRY_NUM,*/
     /*SYS_CAP_SPEC_L2PDU_L2CP_MAX_ACTION_INDEX,*/
     /*SYS_CAP_SPEC_L3PDU_L3HDR_PROTO_ENTRY_NUM,*/
     /*SYS_CAP_SPEC_L3PDU_L4PORT_ENTRY_NUM,*/
     /*SYS_CAP_SPEC_L3PDU_IPDA_ENTRY_NUM,*/
     /*SYS_CAP_SPEC_L3PDU_MAX_ACTION_INDEX,*/
    SYS_CAP_SPEC_SCL_ENTRY_NUM,
    SYS_CAP_SPEC_SCL_HASH_ENTRY_NUM,
    SYS_CAP_SPEC_SCL1_HASH_ENTRY_NUM,
    SYS_CAP_SPEC_SCL0_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_SCL1_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_SCL2_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_SCL3_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL_ENTRY_NUM,
    SYS_CAP_SPEC_ACL_HASH_ENTRY_NUM,
    SYS_CAP_SPEC_ACL0_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL1_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL2_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL3_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL4_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL5_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL6_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL7_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL8_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL9_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL10_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL11_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL12_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL13_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL14_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL15_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL16_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL17_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL18_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL19_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL20_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL21_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL22_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL23_IGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL0_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL1_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL2_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL3_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL4_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL5_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL6_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL7_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL8_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL9_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL10_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_ACL11_EGS_TCAM_ENTRY_NUM,
    SYS_CAP_SPEC_IPFIX_ENTRY_NUM,
    SYS_CAP_SPEC_EFD_FLOW_ENTRY_NUM,
    SYS_CAP_SPEC_MAX_LCHIP_NUM,
    SYS_CAP_SPEC_MAX_PHY_PORT_NUM,
    SYS_CAP_SPEC_MAX_PORT_NUM,
    SYS_CAP_SPEC_MAX_CLASS_ID_NUM,
    SYS_CAP_SPEC_MAX_CHIP_NUM,
    SYS_CAP_ACL_COMPRESS_ETHER_TYPE_NUM,
    SYS_CAP_ACL_COPP_THRD,
    SYS_CAP_ACL_EGRESS_LKUP_NUM,
    SYS_CAP_ACL_FIELD_RANGE,
    SYS_CAP_ACL_HASH_AD_INDEX_OFFSET,
    SYS_CAP_ACL_HASH_CID_KEY,
    SYS_CAP_ACL_HASH_SEL_PROFILE,
    SYS_CAP_ACL_INGRESS_LKUP_NUM,
    SYS_CAP_ACL_LABEL_NUM,
    SYS_CAP_ACL_MAX_CID_VALUE,
    SYS_CAP_ACL_MAX_SESSION,
    SYS_CAP_ACL_IGS_MAX_LOG_ID,
    SYS_CAP_ACL_EGS_MAX_LOG_ID,
    SYS_CAP_ACL_PORT_CLASS_ID_NUM,
    SYS_CAP_ACL_SERVICE_ID_NUM,
    SYS_CAP_ACL_TCAM_CID_PAIR,
    SYS_CAP_ACL_UDF_ENTRY_NUM,
    SYS_CAP_ACL_UDF_KEY_ID_MIN,
    SYS_CAP_ACL_UDF_AD_ID_MAX,
    SYS_CAP_ACL_UDF_AD_ID_MIN,
    SYS_CAP_ACL_SUDF_ENTRY_NUM,
    SYS_CAP_ACL_SUDF_AD_ID_MAX,
    SYS_CAP_ACL_SUDF_AD_ID_MIN,
    SYS_CAP_ACL_UDF_OFFSET_MAX,
    SYS_CAP_ACL_UDF_OFFSET_BYTE_LEN,
    SYS_CAP_ACL_UDF_OFFSET_NUM,
    SYS_CAP_ACL_UDF_OFFSET_TYPE_MAX,
    SYS_CAP_ACL_UDF_LABLE_MAX,
    SYS_CAP_ACL_VLAN_ACTION_SIZE_PER_BUCKET,
    SYS_CAP_ACL_VLAN_CLASS_ID_NUM,
    SYS_CAP_ACL_PORT_BITMAP_NUM,
    SYS_CAP_APS_GROUP_NUM,
    SYS_CAP_AQM_PORT_THRD_HIGN,
    SYS_CAP_AQM_PORT_THRD_LOW,
    SYS_CAP_BFD_INTERVAL_CAM_NUM,
    SYS_CAP_CHANID_DMA_RX0,
    SYS_CAP_CHANID_DMA_RX1,
    SYS_CAP_CHANID_DMA_RX2,
    SYS_CAP_CHANID_DMA_RX3,
    SYS_CAP_CHANID_CPU_MAC0,
    SYS_CAP_CHANID_CPU_MAC1,
    SYS_CAP_CHANID_CPU_MAC2,
    SYS_CAP_CHANID_CPU_MAC3,
    SYS_CAP_CHANID_DROP,
    SYS_CAP_CHANID_ELOG,
    SYS_CAP_CHANID_ELOOP,
    SYS_CAP_CHANID_LOOP_NUM,
    SYS_CAP_CHANID_GMAC_MAX,
    SYS_CAP_CHANID_ILOOP,
    SYS_CAP_CHANID_MAC_DECRYPT,
    SYS_CAP_CHANID_MAC_ENCRYPT,
    SYS_CAP_CHANID_MAX,
    SYS_CAP_CHANID_OAM,
    SYS_CAP_CHANID_OAM1,
    SYS_CAP_CHANID_QCN,
    SYS_CAP_CHANID_RSV,
    SYS_CAP_CHANID_WLAN_DECRYPT0,
    SYS_CAP_CHANID_WLAN_DECRYPT1,
    SYS_CAP_CHANID_WLAN_DECRYPT2,
    SYS_CAP_CHANID_WLAN_DECRYPT3,
    SYS_CAP_CHANID_WLAN_ENCRYPT0,
    SYS_CAP_CHANID_WLAN_ENCRYPT1,
    SYS_CAP_CHANID_WLAN_ENCRYPT2,
    SYS_CAP_CHANID_WLAN_ENCRYPT3,
    SYS_CAP_CHANID_WLAN_REASSEMBLE,
    SYS_CAP_CHANID_HMAC,
    SYS_CAP_CHANID_EUNIT0,
    SYS_CAP_CHANID_EUNIT1,
    SYS_CAP_CHANNEL_NUM,
    SYS_CAP_CPU_OAM_EXCP_NUM,
    SYS_CAP_CPU_REASON_OAM_DEFECT_MESSAGE_BASE,
    SYS_CAP_CPU_REASON_EGS_MAX_EXCP_GID,
    SYS_CAP_CPU_REASON_DEST_ID_BASE_EUNIT,
    SYS_CAP_CPU_REASON_GRP_BASE_EUNIT,
    SYS_CAP_CPU_REASON_GRP_NUM_EUNIT,
    SYS_CAP_CPU_REASON_GRP_Q_NUM_EUNIT,  /*per group used queue num*/
    SYS_CAP_CPU_REASON_SUB_Q_NUM_EUNIT, /*per group valid queue num*/
    SYS_CAP_CPU_REASON_EXCP_NONUC_C2C_PKT,
    SYS_CAP_CPU_REASON_EXCP_NONUC_C2C_PKT2,
    SYS_CAP_DLB_MEMBER_NUM,
    SYS_CAP_DOT1AE_AN_NUM,
    SYS_CAP_DOT1AE_MAX_AN_INUSE_NUM,
    SYS_CAP_DOT1AE_DIVISION_WIDE,
    SYS_CAP_DOT1AE_RX_CHAN_NUM,
    SYS_CAP_DOT1AE_SEC_CHAN_NUM,
    SYS_CAP_DOT1AE_SHIFT_WIDE,
    SYS_CAP_DOT1AE_TX_CHAN_NUM,
    SYS_CAP_DOT1AE_CLEAR_TAG_TYPE_MAX,
    SYS_CAP_DOT1AE_SPI_MAX,
    SYS_CAP_DOT1AE_MAX_AN_BITMAP,
    SYS_CAP_DOT1AE_SA_PER_CHAN,
    SYS_CAP_DOT1AE_STATS_PER_CHAN,
    SYS_CAP_DOT1AE_ENTR_NUM,
    SYS_CAP_EFD_FLOW_DETECT_MAX,
    SYS_CAP_EFD_FLOW_STATS,
    SYS_CAP_EPEDISCARDTYPE_DS_ACL_DIS,
    SYS_CAP_EPEDISCARDTYPE_DS_PLC_DIS,
    SYS_CAP_FID_NUM,
    SYS_CAP_FLOW_HASH_LEVEL_NUM,
    SYS_CAP_GCHIP_CHIP_ID,
    SYS_CAP_GLB_DEST_PORT_NUM_PER_CHIP,
    SYS_CAP_INTR_NUM,
    SYS_CAP_IP_HASH_LEVEL_NUM,
    SYS_CAP_IPFIX_MAX_HASH_SEL_ID,
    SYS_CAP_IPFIX_MAX_SAMPLE_PROFILE,
    SYS_CAP_IPFIX_MIN_AGING_INTERVAL,
    SYS_CAP_IPFIX_MIN_BULK_OP_INTERVAL,
    SYS_CAP_IPFIX_SAMPPLING_PKT_INTERVAL,
    SYS_CAP_IPFIX_FLOW_CNT_THRD,
    SYS_CAP_NPM_IPFIX_CFG_PRF_ID,
    SYS_CAP_NPM_IPFIX_HASH_FIELD_ID,
    SYS_CAP_IPUC_MAX_SNAKE_NUM,
    SYS_CAP_ISOLATION_GROUP_NUM,
    SYS_CAP_ISOLATION_ID_MAX,
    SYS_CAP_ISOLATION_ID_NUM,
    SYS_CAP_ISOLATION_PER_GROUP_ENTRY_NUM,
    SYS_CAP_L2_BLACK_HOLE_ENTRY,
    SYS_CAP_L2_FDB_CAM_NUM,
    SYS_CAP_L2PDU_BASED_BPDU_ENTRY,
    SYS_CAP_L2PDU_BASED_L2HDR_PTL_ENTRY,
    SYS_CAP_L2PDU_BASED_L3TYPE_ENTRY,
    SYS_CAP_L2PDU_BASED_MACDA_ENTRY,
    SYS_CAP_L2PDU_BASED_MACDA_LOW24_ENTRY,
    SYS_CAP_L2PDU_PER_PORT_ACTION_INDEX,
    SYS_CAP_L2PDU_PORT_ACTION_INDEX,
    SYS_CAP_L3IF_ECMP_GROUP_NUM,
    SYS_CAP_L3IF_INNER_ROUTE_MAC_NUM,
    SYS_CAP_L3IF_ROUTER_MAC_ENTRY_NUM,
    SYS_CAP_L3IF_ROUTER_MAC_NUM,
    SYS_CAP_L3IF_ROUTER_MAC_NUM_PER_ENTRY,
    SYS_CAP_L3IF_RSV_L3IF_ID,
    SYS_CAP_L3IF_VLAN_PTR_BASE,
    SYS_CAP_L3PDU_ACTION_INDEX,
    SYS_CAP_L3PDU_BASED_IPDA,
    SYS_CAP_L3PDU_BASED_L3HDR_PROTO,
    SYS_CAP_L3PDU_BASED_PORT,
    SYS_CAP_L3PDU_L3IF_ACTION_INDEX,
    SYS_CAP_L4_USER_UDP_TYPE_VXLAN,
    SYS_CAP_SECURITY_PORT_RSV_NUM,
    SYS_CAP_LEARN_LIMIT_MAX,
    SYS_CAP_LEARN_LIMIT_PROFILE_NUM,
    SYS_CAP_LEARNING_CACHE_MAX_INDEX,
    SYS_CAP_LINKAGG_ALL_MEM_NUM,
    SYS_CAP_LINKAGG_CHAN_ALL_MEM_NUM,
    SYS_CAP_LINKAGG_CHAN_GRP_MAX,
    SYS_CAP_LINKAGG_CHAN_PER_GRP_MEM,
    SYS_CAP_LINKAGG_DYNAMIC_INTERVAL,
    SYS_CAP_LINKAGG_FRAGMENT_SIZE,
    SYS_CAP_LINKAGG_GROUP_NUM,
    SYS_CAP_LINKAGG_MEM_NUM,
    SYS_CAP_LINKAGG_MODE56_DLB_MEM_MAX,
    SYS_CAP_LINKAGG_MODE56_DLB_TID_MAX,
    SYS_CAP_LINKAGG_RR_TID_MAX,
    SYS_CAP_LINKAGG_DLB_FLOW_NUM,
    SYS_CAP_LINKAGG_SPM_FLOW_NUM_GRAN,
    SYS_CAP_LOCAL_SLICE_NUM,
    SYS_CAP_MAC_HASH_LEVEL_NUM,
    SYS_CAP_MIRROR_ACL_ID,
    SYS_CAP_MIRROR_ACL_LOG_ID,
    SYS_CAP_MIRROR_CPU_RX_SPAN_INDEX,
    SYS_CAP_MIRROR_CPU_TX_SPAN_INDEX,
    SYS_CAP_MIRROR_EGRESS_ACL_LOG_INDEX_BASE,
    SYS_CAP_MIRROR_EGRESS_ACL_LOG_PRIORITY,
    SYS_CAP_MIRROR_EGRESS_IPFIX_LOG_INDEX,
    SYS_CAP_MIRROR_EGRESS_L2_SPAN_INDEX_BASE,
    SYS_CAP_MIRROR_EGRESS_L3_SPAN_INDEX_BASE,
    SYS_CAP_MIRROR_INGRESS_ACL_LOG_INDEX_BASE,
    SYS_CAP_MIRROR_INGRESS_ACL_LOG_PRIORITY,
    SYS_CAP_MIRROR_INGRESS_IPFIX_LOG_INDEX,
    SYS_CAP_MIRROR_INGRESS_L2_SPAN_INDEX_BASE,
    SYS_CAP_MIRROR_INGRESS_L3_SPAN_INDEX_BASE,
    SYS_CAP_MIRROR_MEMBER_NUM,
    SYS_CAP_MONITOR_BUFFER_RSV_PROF,
    SYS_CAP_MONITOR_DIVISION_WIDE,
    SYS_CAP_MONITOR_LATENCY_MAX_LEVEL,
    SYS_CAP_MONITOR_MAX_CHAN_PER_SLICE,
    SYS_CAP_MONITOR_MAX_CHANNEL,
    SYS_CAP_MONITOR_SHIFT_WIDE,
    SYS_CAP_MONITOR_SYNC_CNT,
    SYS_CAP_MONITOR_BUFFER_MAX_THRD,
    SYS_CAP_MONITOR_ON_DROP_SPAN_INDEX,
    SYS_CAP_MPLS_INNER_ROUTE_MAC_NUM,
    SYS_CAP_MPLS_MAX_LABEL,
    SYS_CAP_MPLS_MAX_LABEL_SPACE,
    SYS_CAP_MPLS_MAX_OAM_CHK_TYPE,
    SYS_CAP_MPLS_MAX_TPID_INDEX,
    SYS_CAP_NETWORK_CHANNEL_NUM,
    SYS_CAP_NEXTHOP_MAX_CHIP_NUM,
    SYS_CAP_NEXTHOP_PORT_NUM_PER_CHIP,
    SYS_CAP_NH_CW_NUM,
    SYS_CAP_NH_DROP_DESTMAP,
    SYS_CAP_NH_DSMET_BITMAP_MAX_PORT_ID,
    SYS_CAP_NH_ECMP_GROUP_ID_NUM,
    SYS_CAP_NH_ECMP_MEMBER_NUM,
    SYS_CAP_NH_ECMP_RR_GROUP_NUM,
    SYS_CAP_NH_ILOOP_MAX_REMOVE_WORDS,
    SYS_CAP_NH_IP_TUNNEL_INVALID_IPSA_NUM,
    SYS_CAP_NH_IP_TUNNEL_IPV4_IPSA_NUM,
    SYS_CAP_NH_IP_TUNNEL_IPV6_IPSA_NUM,
    SYS_CAP_NH_L2EDIT_VLAN_PROFILE_NUM,
    SYS_CAP_NH_MAX_ECPN,
    SYS_CAP_NH_OUTER_L2_EDIT_NUM,
    SYS_CAP_NH_DESTMAP_PROFILE_NUM,
    SYS_CAP_NH_VXLAN_PROFLLE_NUM,
    SYS_CAP_NH_MC_PBMP_NUM,
    SYS_CAP_NPM_SESSION_NUM,
    SYS_CAP_OAM_BFD_IPV6_MAX_IPSA_NUM,
    SYS_CAP_OAM_DEFECT_NUM,
    SYS_CAP_OAM_MEP_ID,
    SYS_CAP_OAM_MEP_NUM_PER_CHAN,
    SYS_CAP_OVERLAY_TUNNEL_IP_INDEX,
    SYS_CAP_PARSER_L2_PROTOCOL_USER_ENTRY,
    SYS_CAP_PARSER_L3_PROTOCOL_USER_ENTRY,
    SYS_CAP_PARSER_L3FLEX_BYTE_SEL,
    SYS_CAP_PARSER_L4_APP_DATA_CTL_ENTRY,
    SYS_CAP_PARSER_UPF_OFFSET,
    SYS_CAP_PER_SLICE_PORT_NUM,
    SYS_CAP_PER_SLICE_CHANNEL_NUM,
    SYS_CAP_PER_DP_CHANNEL_NUM,
    SYS_CAP_PER_DP_PHY_CHANNEL_NUM,
    SYS_CAP_PER_DP_PORT_NUM,
    SYS_CAP_PER_DP_PHY_PORT_NUM,
    SYS_CAP_PHY_PORT_NUM_PER_SLICE,
    SYS_CAP_PKT_CPU_QDEST_BY_DMA,
    SYS_CAP_PKT_STRIP_PKT_LEN,
    SYS_CAP_PKT_TRUNCATED_LEN,
    SYS_CAP_PORT_NUM,
    SYS_CAP_PORT_NUM_GLOBAL,
    SYS_CAP_PORT_NUM_PER_CHIP,
    SYS_CAP_PORT_TCAM_TYPE_NUM,
    SYS_CAP_PORT_BITMAP_NUM,
    SYS_CAP_PORT_MISC_PORT_MASK,
    SYS_CAP_PORT_MIN_FRAMESIZE_MIN_VALUE,
    SYS_CAP_PORT_MIN_FRAMESIZE_MAX_VALUE,
    SYS_CAP_PORT_MAX_FRAMESIZE_MIN_VALUE,
    SYS_CAP_PORT_MAX_FRAMESIZE_MAX_VALUE,
    SYS_CAP_PTP_CAPTURED_RX_SEQ_ID,
    SYS_CAP_PTP_CAPTURED_RX_SOURCE,
    SYS_CAP_PTP_CAPTURED_TX_SEQ_ID,
    SYS_CAP_PTP_FRC_VALUE_SECOND,
    SYS_CAP_PTP_MAX_PTP_ID,
    SYS_CAP_PTP_MAX_DOMAIN_ID,
    SYS_CAP_PTP_NS_OR_NNS_VALUE,
    SYS_CAP_PTP_MIN_OFFSET_RELOAD,
    SYS_CAP_PTP_MAX_SESSION_ID,
    SYS_CAP_PTP_MAX_INTERVAL,
    SYS_CAP_PTP_MIN_INTERVAL,
    SYS_CAP_PTP_RC_QUANTA,
    SYS_CAP_PTP_SECONDS_OF_EACH_WEEK,
    SYS_CAP_PTP_SYNC_CODE_BIT,
    SYS_CAP_PTP_SYNC_PULSE_FREQUENCY_HZ,
    SYS_CAP_PTP_TAI_TO_GPS_SECONDS,
    SYS_CAP_PTP_TOD_1PPS_DELAY,
    SYS_CAP_PTP_TOD_ADJUSTING_THRESHOLD,
    SYS_CAP_PTP_TOD_ADJUSTING_TOGGLE_STEP,
    SYS_CAP_PTP_TOD_PULSE_HIGH_LEVEL,
    SYS_CAP_PTP_DOMAIN_0_RTC,
    SYS_CAP_PTP_DOMAIN_1_RTC,
    SYS_CAP_PTP_FREE_RTC_ID,
    SYS_CAP_PTP_DOMAIN_0,
    SYS_CAP_PTP_DOMAIN_1,
    SYS_CAP_PTP_PER_CORE_INDEX_START,
    SYS_CAP_PVLAN_COMMUNITY_ID_NUM,
    SYS_CAP_QOS_BASE_QUEUE_GRP_NUM,
    SYS_CAP_QOS_BASE_QUEUE_NUM,
    SYS_CAP_QOS_CLASS_COS_DOMAIN_MAX,
    SYS_CAP_QOS_CLASS_DSCP_DOMAIN_MAX,
    SYS_CAP_QOS_CLASS_EXP_DOMAIN_MAX,
    SYS_CAP_QOS_CLASS_PRIORITY_MAX,
    SYS_CAP_QOS_CLASS_TABLE_MAP_ID_MAX,
    SYS_CAP_QOS_CLASS_OBM_DSCP_DOMAIN_MAX,
    SYS_CAP_QOS_CLASS_OBM_COS_DOMAIN_MAX,
    SYS_CAP_QOS_CLASS_OBM_PRIORITY_MAX,
    SYS_CAP_QOS_CONGEST_LEVEL_NUM,
    SYS_CAP_QOS_EXT_GRP_BASE_NUM,
    SYS_CAP_QOS_EXT_QUEUE_GRP_NUM,
    SYS_CAP_QOS_GROUP_NUM,
    SYS_CAP_QOS_GROUP_SHAPE_PROFILE,
    SYS_CAP_QOS_GRP_SHP_CBUCKET_NUM,
    SYS_CAP_QOS_MAX_SHAPE_BURST,
    SYS_CAP_QOS_MIN_SHAPE_BURST,
    SYS_CAP_QOS_MISC_QUEUE_NUM,
    SYS_CAP_QOS_NORMAL_QUEUE_NUM,
    SYS_CAP_QOS_OAM_QUEUE_NUM,
    SYS_CAP_QOS_PHB_OFFSET_NUM,
    SYS_CAP_QOS_POLICER_ACTION_PROFILE_NUM,
    SYS_CAP_QOS_POLICER_SVC_ACTION_PROFILE_NUM,
    SYS_CAP_QOS_POLICER_CBS,
    SYS_CAP_QOS_POLICER_COPP_PROFILE_NUM,
    SYS_CAP_QOS_POLICER_MFP_PROFILE_NUM,
    SYS_CAP_QOS_POLICER_SVC_PROFILE_NUM,
    SYS_CAP_QOS_POLICER_POLICER_NUM,
    SYS_CAP_QOS_POLICER_SVC_POLICER_NUM,
    SYS_CAP_QOS_POLICER_PPS_PACKET_BYTES,
    SYS_CAP_QOS_POLICER_PROF_TBL_NUM,
    SYS_CAP_QOS_POLICER_PROFILE_NUM,
    SYS_CAP_QOS_POLICER_RATE_KBPS,
    SYS_CAP_QOS_POLICER_RATE_PPS,
    SYS_CAP_QOS_POLICER_SUPPORTED_FREQ_NUM,
    SYS_CAP_QOS_POLICER_TOKEN_RATE_BIT_WIDTH,
    SYS_CAP_QOS_POLICER_TOKEN_THRD_SHIFTS_WIDTH,
    SYS_CAP_QOS_POLICER_MAX_COS_LEVEL,
    SYS_CAP_QOS_POLICER_GROUP_NUM,
    SYS_CAP_QOS_POLICER_SVC_TOKEN_RATE,
    SYS_CAP_QOS_POLICER_SVC_TOKEN_THRD,
    SYS_CAP_QOS_PORT_AQM_FREQ,
    SYS_CAP_QOS_PORT_POLICER_NUM,
    SYS_CAP_QOS_PORT_POLICER_NUM_4Q,
    SYS_CAP_QOS_PORT_POLICER_NUM_8Q,
    SYS_CAP_QOS_QUEUE_BASE_EXCP,
    SYS_CAP_QOS_QUEUE_BASE_EXT,
    SYS_CAP_QOS_QUEUE_BASE_MISC,
    SYS_CAP_QOS_QUEUE_BASE_NETWORK_MISC,
    SYS_CAP_QOS_QUEUE_BASE_NORMAL,
    SYS_CAP_QOS_QUEUE_BASE_CTL,
    SYS_CAP_QOS_QUEUE_BASE_16Q,
    SYS_CAP_QOS_QUEUE_BASE_EUNIT,
    SYS_CAP_QOS_QUEUE_GRP_BASE_16Q,
    SYS_CAP_QOS_QUEUE_BUCKET,
    SYS_CAP_QOS_QUEUE_GRP_NUM_FOR_CPU_REASON,
    SYS_CAP_QOS_QUEUE_INVALID_GROUP,
    SYS_CAP_QOS_QUEUE_METER_PROFILE,
    SYS_CAP_QOS_QUEUE_NUM,
    SYS_CAP_QOS_QUEUE_NUM_PER_CHAN,
    SYS_CAP_QOS_QUEUE_NUM_PER_EXT_GRP,
    SYS_CAP_QOS_QUEUE_NUM_PER_GRP,
    SYS_CAP_QOS_QUEUE_NUM_PER_GRP_16Q,
    SYS_CAP_QOS_QUEUE_OFFSET_EXT,
    SYS_CAP_QOS_QUEUE_OFFSET_NETWORK,
    SYS_CAP_QOS_QUEUE_PIR_BUCKET,
    SYS_CAP_QOS_QUEUE_SHAPE_PROFILE,
    SYS_CAP_QOS_QUEUE_SHAPE_PIR_PROFILE,
    SYS_CAP_QOS_QUEUE_WEIGHT_BASE,
    SYS_CAP_QOS_QUEUE_MAX_DROP_THRD,
    SYS_CAP_QOS_QUEUE_MAX_DROP_PROB,
    SYS_CAP_QOS_QUEUE_DROP_WTD_PROFILE_NUM,
    SYS_CAP_QOS_QUEUE_DROP_WRED_PROFILE_NUM,
    SYS_CAP_QOS_DROP_IGS_DEFAULT_POOL_SIZE,
    SYS_CAP_QOS_DROP_EGS_DEFAULT_POOL_SIZE,
    SYS_CAP_QOS_DROP_TOTAL_POOL_SIZE,
    SYS_CAP_QOS_DROP_TOTAL_UC_POOL_SIZE,
    SYS_CAP_QOS_DROP_TOTAL_NON_UC_POOL_SIZE,
    SYS_CAP_QOS_DROP_MRM_TOTAL_POOL_SIZE,
    SYS_CAP_QOS_DROP_OBM_TOTAL_POOL_SIZE,
    SYS_CAP_QOS_REASON_C2C_MAX_QUEUE_NUM,
    SYS_CAP_QOS_SCHED_MAX_QUE_WEITGHT,
    SYS_CAP_QOS_SCHED_WEIGHT_BASE,
    SYS_CAP_QOS_SCHED_MAX_QUE_CLASS,
    SYS_CAP_QOS_SCHED_MAX_EXT_QUE_CLASS,
    SYS_CAP_QOS_SHP_BUCKET_CIR_PASS0,
    SYS_CAP_QOS_SHP_BUCKET_CIR_PASS1,
    SYS_CAP_QOS_SHP_BUCKET_PIR,
    SYS_CAP_QOS_SHP_BUCKET_PIR_PASS0,
    SYS_CAP_QOS_SHP_BUCKET_PIR_PASS1,
    SYS_CAP_QOS_SHP_FULL_TOKENS,
    SYS_CAP_QOS_SHP_PPS_PACKET_BYTES,
    SYS_CAP_QOS_SHP_PPS_SHIFT,
    SYS_CAP_QOS_SHP_RATE,
    SYS_CAP_QOS_SHP_RATE_PPS,
    SYS_CAP_QOS_SHP_TOKEN_RATE,
    SYS_CAP_QOS_SHP_TOKEN_RATE_BIT_WIDTH,
    SYS_CAP_QOS_SHP_TOKEN_RATE_FRAC,
    SYS_CAP_QOS_SHP_TOKEN_THRD,
    SYS_CAP_QOS_SHP_TOKEN_THRD_SHIFT,
    SYS_CAP_QOS_SHP_TOKEN_THRD_SHIFTS_WIDTH,
    SYS_CAP_QOS_SHP_UPDATE_UNIT,
    SYS_CAP_QOS_SHP_WEIGHT_BASE,
    SYS_CAP_QOS_SUB_GRP_NUM_PER_GRP,
    SYS_CAP_QOS_VLAN_POLICER_NUM,
    SYS_CAP_QOS_REP_QUEUE_NUM,
    SYS_CAP_QOS_CTL_QUEUE_NUM,
    SYS_CAP_QOS_LX_GRP_NODE_NUM,
    SYS_CAP_QOS_QUE_GRP_NODE_NUM,
    SYS_CAP_QOS_L0_GRP_NUM,
    SYS_CAP_QOS_L1_GRP_NUM,
    SYS_CAP_QOS_L2_GRP_NUM,
    SYS_CAP_QOS_L3_GRP_NUM,
    SYS_CAP_QOS_QUE_GRP_NUM,
    SYS_CAP_QOS_LVL_GRP_NUM,
    SYS_CAP_RANDOM_LOG_RATE,
    SYS_CAP_RANDOM_LOG_THRESHOD,
    SYS_CAP_RANDOM_LOG_EGS_SHIFT,
    SYS_CAP_RANDOM_LOG_SHIFT,
    SYS_CAP_REASON_GRP_QUEUE_NUM,
    SYS_CAP_REASON_TOTAL_QUEUE_NUM,
    SYS_CAP_REASON_TOTAL_QUEUE_NUM_UC,
    SYS_CAP_RPF_IF_NUM,
    SYS_CAP_RPF_PROFILE_NUM,
    SYS_CAP_SCL_ACL_CONTROL_PROFILE,
    SYS_CAP_SCL_AD_FIELD_POS_IS_HALF,
    SYS_CAP_SCL_BY_PASS_VLAN_PTR,
    SYS_CAP_SCL_DS_AD_FIELD_PO_AD_INDEX,
    SYS_CAP_SCL_HASH_SEL_ID,
    SYS_CAP_SCL_LABEL_FOR_IPSG,
    SYS_CAP_SCL_LABEL_FOR_VLAN_CLASS,
    SYS_CAP_SCL_LABEL_FOR_SRV6,
    SYS_CAP_SCL_LABEL_NUM,
    SYS_CAP_SCL_IGS_TCAM_NUM,
    SYS_CAP_SCL_TCAM_NUM,
    SYS_CAP_SCL_VLAN_ACTION_RESERVE_NUM,
    SYS_CAP_SCL_FWD_TYPE,
    SYS_CAP_SCL_SERVICE_ID_NUM,
    SYS_CAP_SCL_HASH_NUM,
    SYS_CAP_SCL_DEFAULT_ENTRY_BASE,
    SYS_CAP_SCL_ACTION_SIZE,
    SYS_CAP_SCL_TUNNEL_LPORT_MAX,
    SYS_CAP_SCL_HASH_SEL_ID_NUM,
    SYS_CAP_STATS_RAM_NUM,
    SYS_CAP_STATS_GLOBAL_RAM_NUM,
    SYS_CAP_STATS_PRIVATE_IPE_RAM_NUM,
    SYS_CAP_STATS_PRIVATE_EPE_RAM_NUM,
    SYS_CAP_STATS_ACL0_SIZE,
    SYS_CAP_STATS_ACL1_SIZE,
    SYS_CAP_STATS_ACL2_SIZE,
    SYS_CAP_STATS_ACL3_SIZE,
    SYS_CAP_STATS_ACL4_SIZE,
    SYS_CAP_STATS_ACL5_SIZE,
    SYS_CAP_STATS_ACL6_SIZE,
    SYS_CAP_STATS_ACL7_SIZE,
    SYS_CAP_STATS_ACL8_SIZE,
    SYS_CAP_STATS_ACL9_SIZE,
    SYS_CAP_STATS_ACL10_SIZE,
    SYS_CAP_STATS_ACL11_SIZE,
    SYS_CAP_STATS_ACL12_SIZE,
    SYS_CAP_STATS_ACL13_SIZE,
    SYS_CAP_STATS_ACL14_SIZE,
    SYS_CAP_STATS_ACL15_SIZE,
    SYS_CAP_STATS_ACL16_SIZE,
    SYS_CAP_STATS_ACL17_SIZE,
    SYS_CAP_STATS_ACL18_SIZE,
    SYS_CAP_STATS_ACL19_SIZE,
    SYS_CAP_STATS_ACL20_SIZE,
    SYS_CAP_STATS_ACL21_SIZE,
    SYS_CAP_STATS_ACL22_SIZE,
    SYS_CAP_STATS_ACL23_SIZE,
    SYS_CAP_STATS_CGMAC_RAM_MAX,
    SYS_CAP_STATS_DEQUEUE_SIZE,
    SYS_CAP_STATS_ECMP_RESERVE_SIZE,
    SYS_CAP_STATS_EGS_ACL0_SIZE,
    SYS_CAP_STATS_EGS_ACL1_SIZE,
    SYS_CAP_STATS_EGS_ACL2_SIZE,
    SYS_CAP_STATS_EGS_ACL3_SIZE,
    SYS_CAP_STATS_EGS_ACL4_SIZE,
    SYS_CAP_STATS_EGS_ACL5_SIZE,
    SYS_CAP_STATS_EGS_ACL6_SIZE,
    SYS_CAP_STATS_EGS_ACL7_SIZE,
    SYS_CAP_STATS_EGS_ACL8_SIZE,
    SYS_CAP_STATS_EGS_ACL9_SIZE,
    SYS_CAP_STATS_EGS_ACL10_SIZE,
    SYS_CAP_STATS_EGS_ACL11_SIZE,
    SYS_CAP_STATS_ENQUEUE_SIZE,
    SYS_CAP_STATS_IPE_FWD_SIZE,
    SYS_CAP_STATS_IPE_IF_SIZE,
    SYS_CAP_STATS_POLICER_SIZE,
    SYS_CAP_STATS_RAM_GLOBAL_SIZE,
    SYS_CAP_STATS_RAM_PRIVATE_SIZE,
    SYS_CAP_STATS_XQMAC_PORT_NUM,
    SYS_CAP_STATS_XQMAC_RAM_NUM,
    SYS_CAP_STATS_DMA_BLOCK_SIZE,
    SYS_CAP_STATS_DMA_BLOCK_NUM,
    SYS_CAP_STATS_DMA_PP_BLOCK_NUM,
    SYS_CAP_STATS_DMA_QUEUE_BLOCK_ID,
    SYS_CAP_STATS_DMA_QUEUE_MC_BLOCK_ID,
    SYS_CAP_STATS_DMA_IO_TIMER,
    SYS_CAP_STATS_WB_STATS_ID_NUM,
    SYS_CAP_STATS_HW_LOCAL_STATSPTR_BIT_NUM,
    SYS_CAP_STATS_TOTAL_SIZE,
    SYS_CAP_STK_GLB_DEST_PORT_NUM,
    SYS_CAP_STK_MAX_GCHIP,
    SYS_CAP_STK_MAX_LPORT,
    SYS_CAP_STK_PORT_FWD_PROFILE_NUM,
    SYS_CAP_STK_SGMAC_GROUP_NUM,
    SYS_CAP_STK_TRUNK_DLB_MAX_MEMBERS,
    SYS_CAP_STK_TRUNK_STATIC_MAX_MEMBERS,
    SYS_CAP_STK_TRUNK_MAX_ID,
    SYS_CAP_STK_TRUNK_MAX_NUM,
    SYS_CAP_STK_TRUNK_MEMBERS,
    SYS_CAP_STMCTL_DEFAULT_THRD,
    SYS_CAP_STMCTL_DIV_PULSE,
    SYS_CAP_STMCTL_MAC_COUNT,
    SYS_CAP_STMCTL_MAX_KBPS,
    SYS_CAP_STMCTL_MAX_PPS,
    SYS_CAP_STMCTL_UPD_FREQ,
    SYS_CAP_HMAC_SHA_KEY_NUM,
    SYS_CAP_STP_STATE_ENTRY_NUM,
    SYS_CAP_SYNC_ETHER_CLOCK,
    SYS_CAP_SYNC_ETHER_DIVIDER,
    SYS_CAP_VLAN_BITMAP_NUM,
    SYS_CAP_VLAN_PROFILE_ID,
    SYS_CAP_VLAN_RANGE_EN_BIT_POS,
    SYS_CAP_VLAN_RANGE_ENTRY_NUM,
    SYS_CAP_VLAN_RANGE_TYPE_BIT_POS,
    SYS_CAP_VLAN_STATUS_ENTRY_BITS,
    SYS_CAP_VLAN_RANGE_BLOCK_NUM,
    SYS_VLAN_RESERVE_NUM,
    SYS_CAP_MAX_VLAN_PTR,
    SYS_CAP_WLAN_PER_SSI_NUM,
    SYS_CAP_WLAN_PER_TUNNEL_NUM,
    SYS_CAP_SERVICE_ID_NUM,
    SYS_CAP_NPM_MAX_TS_OFFSET,
    SYS_CAP_IPEDISCARD_DS_PLC_DIS,
    SYS_CAP_IPEDISCARD_DS_ACL_DIS,
    SYS_CAP_IPEDISCARD_DOT1AE_CHK,
    SYS_CAP_IPEDISCARD_OAM_DISABLE,
    SYS_CAP_IPEDISCARD_OAM_NOT_FOUND,
    SYS_CAP_IPEDISCARD_CFLAX_SRC_ISOLATE_DIS,
    SYS_CAP_IPEDISCARD_OAM_ETH_VLAN_CHK,
    SYS_CAP_IPEDISCARD_OAM_BFD_TTL_CHK,
    SYS_CAP_IPEDISCARD_OAM_FILTER_DIS,
    SYS_CAP_IPEDISCARD_TRILL_CHK,
    SYS_CAP_IPEDISCARD_WLAN_CHK,
    SYS_CAP_IPEDISCARD_TUNNEL_ECN_DIS,
    SYS_CAP_IPEDISCARD_EFM_DIS,
    SYS_CAP_IPEDISCARD_ILOOP_DIS,
    SYS_CAP_IPEDISCARD_MPLS_ENTROPY_LABEL_CHK,
    SYS_CAP_IPEDISCARD_MPLS_TP_MCC_SCC_DIS,
    SYS_CAP_IPEDISCARD_MPLS_MC_PKT_ERROR,
    SYS_CAP_IPEDISCARD_L2_EXCPTION_DIS,
    SYS_CAP_IPEDISCARD_NAT_PT_CHK,
    SYS_CAP_IPEDISCARD_SD_CHECK_DIS,
    SYS_CAP_IPEDISCARD_INT_CHK,
    SYS_CAP_IPEDISCARD_USERID_CHK,

    SYS_CAP_LINKAGG_RR_MAX_MEM_NUM,
    SYS_CAP_VLAN_STATUS_NUM,
    SYS_CAP_IPFIX_MEMORY_SHARE,
    SYS_CAP_NH_MAX_LOGIC_DEST_PORT,
    SYS_CAP_NH_MAX_LOGIC_DEST_PORT_EXT,
    SYS_CAP_NH_LOGIC_DEST_PORT_EXT_BASE,
    SYS_CAP_MAX_LOGIC_PORT,
    SYS_CAP_DMPS_SERDES_NUM_PER_SLICE,
    SYS_CAP_DMPS_HSS28G_NUM_PER_SLICE,
    SYS_CAP_DMPS_HSS15G_NUM_PER_SLICE,
    SYS_CAP_DMPS_HSS_NUM,
    SYS_CAP_DMPS_CALENDAR_CYCLE,

    SYS_CAP_MAC_NUM_PER_DP,
    SYS_CAP_MAC_NUM_PER_CORE,
    SYS_CAP_MAC_NUM_PER_QM,

    SYS_CAP_DP_MAX_NUM,
    SYS_CAP_CORE_MAX_NUM,

    SYS_CAP_DMA_MAX_CHAN_ID,
    SYS_CAP_DMA_TCAM_SCAN_ERROR_INTR,
    SYS_CAP_INTR_MAX_COUNT,
    SYS_CAP_LB_HASH_SELECT_NUM,
    SYS_CAP_LB_HASH_EXT_SELECT_NUM,
    SYS_CAP_LB_HASH_PROFILE_ID_MAX,
    SYS_CAP_MDIO_CTL_NUM,
    SYS_CAP_MDIO_CTL_NUM_PER_CORE,
    SYS_CAP_MDIO_BUS_NUM_PER_CORE,
    SYS_CAP_I2C_CTL_NUM,
    SYS_CAP_I2C_CTL_NUM_PER_CORE,
    SYS_CAP_I2C_REF_CLOCK,
    SYS_CAP_GPIO_NUM,
    SYS_CAP_GPIO_NUM_PER_CORE,
    SYS_CAP_SGPIO_NUM,

    SYS_CAP_CHANID_LOO0,
    SYS_CAP_CHANID_LOO1,
    SYS_CAP_CHANID_LOO2,
    SYS_CAP_CHANID_LOO3,
    SYS_CAP_CHANID_DMA_TX0,
    SYS_CAP_CHANID_DMA_TX1,
    SYS_CAP_CHANID_DMA_NUM,

    SYS_CAP_MAX_MAC_NUM_PER_TXQM,
    SYS_CAP_TXQM_NUM_PER_DP,
    SYS_CAP_MAX_MAC_NUM_PER_DP,
    SYS_CAP_MAX_MAC_NUM,
    SYS_CAP_MAX_MISC_CHANNEL,
    SYS_CAP_DPPORT_NUM_PER_TXQM,

    SYS_CAP_INTERNAL_PORT_START,
    SYS_CAP_INTERNAL_PORT_END,
    /*rsv port*/
    SYS_CAP_RSV_PORT_START,
    SYS_CAP_RSV_PORT_WLAN_ENCAP,
    SYS_CAP_RSV_PORT_WLAN_E2ILOOP,
    SYS_CAP_RSV_PORT_CAWAP_DECRYPT0_ID,
    SYS_CAP_RSV_PORT_CAWAP_DECRYPT1_ID,
    SYS_CAP_RSV_PORT_CAWAP_DECRYPT2_ID,
    SYS_CAP_RSV_PORT_CAWAP_DECRYPT3_ID,
    SYS_CAP_RSV_PORT_CAWAP_ENCRYPT0_ID,
    SYS_CAP_RSV_PORT_CAWAP_ENCRYPT1_ID,
    SYS_CAP_RSV_PORT_CAWAP_ENCRYPT2_ID,
    SYS_CAP_RSV_PORT_CAWAP_ENCRYPT3_ID,
    SYS_CAP_RSV_PORT_CAWAP_REASSEMBLE_ID,
    SYS_CAP_RSV_PORT_MAC_ENCRYPT_ID,
    SYS_CAP_RSV_PORT_MAC_DECRYPT_ID,
    SYS_CAP_RSV_PORT_EUNIT0_ID,
    SYS_CAP_RSV_PORT_EUNIT1_ID,
    SYS_CAP_RSV_PORT_MOD_ID,
    SYS_CAP_RSV_PORT_BYPASS_IPE_ID,
    SYS_CAP_RSV_PORT_E2ILOOP_ID,
    SYS_CAP_RSV_PORT_DROP_ID,
    SYS_CAP_RSV_PORT_OAM_CPU_ID,
    SYS_CAP_RSV_PORT_OAM_CPU1_ID,
    SYS_CAP_RSV_PORT_ELOOP_ID,
    SYS_CAP_RSV_PORT_ELOOP1_ID,
    SYS_CAP_RSV_PORT_IP_TUNNEL,
    SYS_CAP_RSV_PORT_MIRROR,
    SYS_CAP_RSV_PORT_ILOOP_ID,
    SYS_CAP_RSV_PORT_ILOOP1_ID,
    SYS_CAP_RSV_PORT_TO_CPU,
    SYS_CAP_RSV_PORT_HMAC,
    SYS_CAP_RSV_PORT_SPINE_LEAF_PORT,
    SYS_CAP_IPFIX_LONG_KEY_NUM,
    SYS_CAP_IPFIX_AD_NUM,
    SYS_CAP_MC_BITMAP_MAX_PORT,
    SYS_CAP_DMA_MAX_TBL_SIZE,
    SYS_CAP_CPUMAC_NUM_PER_DP,
    SYS_CAP_CPUMAC_NUM_PER_CORE,
    SYS_CAP_CPUMAC_ID_MIN,
    SYS_CAP_CPUMAC_ID_MAX,
    SYS_CAP_BASE_DISCARD_EPE_START,
    SYS_CAP_EUNIT_NUM,
    SYS_CAP_PACKET_HEADER_LEN,
    SYS_CAP_DMA_REPORT_TYPE_IRM0,
    SYS_CAP_DMA_REPORT_TYPE_IRM1,
    SYS_CAP_DMA_REPORT_TYPE_ERM_STATS,
    SYS_CAP_DMA_REPORT_TYPE_ERM_EVENT,
    SYS_CAP_DMA_REPORT_TYPE_LATENCY_STATS,
    SYS_CAP_DMA_REPORT_TYPE_LATENCY_EVENT,
    SYS_CAP_DMA_REPORT_TYPE_EFD,
    SYS_CAP_DMA_REPORT_TYPE_DLB,
    SYS_CAP_DMA_REPORT_TYPE_OAM,
    SYS_CAP_DMA_REPORT_TYPE_SPNOAM_LOCAL,
    SYS_CAP_DMA_REPORT_TYPE_SPNOAM_MASTER,
    SYS_CAP_DMA_REPORT_TYPE_LEARNING,
    SYS_CAP_DMA_REPORT_TYPE_AGING,
    SYS_CAP_DMA_REPORT_TYPE_FDB_DUMP,
    SYS_CAP_CHIP_TEMP_SENSOR_NUM,
    SYS_CAP_CHIP_VOL_SENSOR_NUM,
    SYS_CAP_LB_HASH_MAX_SEL_NUM,
    SYS_CAP_XPIPE_PORT_NUM,
    /*flexe*/
    SYS_CAP_FLEXE_MAX_SHIM_CNT,
    SYS_CAP_FLEXE_MAX_INST_CNT,
    SYS_CAP_FLEXE_MAX_CYCLE,
    SYS_CAP_FLEXE_MAX_SLOT_PER_INST,
    SYS_CAP_FLEXE_MAX_OH_PHY_INST_CNT,
    SYS_CAP_FLEXE_MAX_CLIENT,
    SYS_CAP_FLEXE_MAX_GROUP,

    SYS_CAP_MAX
};
/*Dot1ae*/

enum sys_sub_feature_e
{
    SYS_FEATURE_OAM_ETH,
    SYS_FEATURE_OAM_Y1731,
    SYS_FEATURE_QOS_HQOS,
    SYS_FEATURE_QOS_XIPIP,
    SYS_FEATURE_HMAC,

    SYS_SUB_FEATURE_MAX
};
typedef enum sys_sub_feature_e sys_sub_feature_t;

struct sys_usw_mchip_1ae_s
{
    int32 (*add_sc_to_asic)(uint8 lchip, void* sys_chan);
    int32 (*add_sa_to_asic)(uint8 lchip, void* sys_chan, uint8 sa_idx, uint32 update_flag);
    int32 (*build_sc_index)(uint8 lchip, void* sys_chan);
    int32 (*free_sc_index)(uint8 lchip, void* sys_chan);
    int32 (*reset_sec_chan_cfg)(uint8 lchip, void* sys_chan);
    int32 (*get_en_sec_chan)(uint8 lchip, void* bind_sc);
    int32 (*en_sec_chan)(uint8 lchip, void* bind_sc);
    int32 (*update_sc_chan)(uint8 lchip, void* sys_chan, void* sc);
    int32 (*unbind_sec_chan)(uint8 lchip, void* bind_sc);
    int32 (*set_glb_cfg)(uint8 lchip, void* p_glb_cfg);
    int32 (*get_glb_cfg)(uint8 lchip, void* p_glb_cfg);
    int32 (*get_stats)(uint8 lchip, uint32 sc_chan_id, void* stats);
    int32 (*sync_dma_stats)(uint8 lchip, void* p_data);
    int32 (*register_init)(uint8 lchip);
    int32 (*add_entry)(uint8 lchip, void* p_ctc_entry);
    int32 (*remove_entry)(uint8 lchip, uint32 entry_id);
    int32 (*show_entry)(uint8 lchip, void* param);
    int32 (*chk_pp_id)(uint8 lchip, uint32 chan_id);
    int32 (*set_hash_field_sel)(uint8 lchip, void* hash_sel);
    int32 (*get_hash_field_sel)(uint8 lchip, void* hash_sel);
    int32 (*set_chan_ctl)(uint8 lchip, void* sys_chan);
    int32 (*wb_chan_restore)(uint8 lchip, void* sys_chan);
    int32 (*entry_hash_init)(uint8 lchip);
    int32 (*entry_hash_deinit)(uint8 lchip);
};
typedef struct sys_usw_mchip_1ae_s sys_usw_mchip_1ae_t;
/*Linkagg*/
struct sys_usw_mchip_lag_s
{
    int32 (*destroy)(uint8 lchip, void* p_lag_group);
    int32 (*add_nonuc_ports)(uint8 lchip,  void* p_lag_group, uint32 gport, uint8 nonuc_block_en);
    int32 (*remove_nonuc_ports)(uint8 lchip, void* p_lag_group, uint32 gport, uint8 nonuc_block_en);
    int32 (*dlb_init)(uint8 lchip);
    int32 (*dlb_set_cfg)(uint8 lchip,void* p_dlb_cfg);
    int32 (*dlb_get_cfg)(uint8 lchip,void* p_dlb_cfg);
    int32 (*set_lsh)(uint8 lchip, void* p_lag_group, uint32 fail_port, void* p_ports);
    int32 (*channel_update_nonuc_ports)(uint8 lchip, bool is_add_port, uint16 chan_id, uint32* mem_bmp);
	int32 (*bind_mirror)(uint8 lchip, uint16 tid, uint8 is_add);
    int32 (*update_mirror_dest)(uint8 lchip, uint16 tid, uint8 is_set);
    int32 (*replace_nonuc_ports)(uint8 lchip, void* p_lag_group);
    int32 (*update_nonuc_ports_by_pp)(uint8 lchip, void* p_lag_group, uint32 gport, uint32* port_bitmap_old, uint32* port_bitmap_new, uint8 op);
    int32 (*loop_chan_lag_en)(uint8 lchip, uint32 enable);
};
typedef struct sys_usw_mchip_lag_s sys_usw_mchip_lag_t;
/*DMPS*/
struct sys_usw_mchip_dmps_s
{
    /* DMPS */
    int32 (*mac_set_property)(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 value);
    int32 (*mac_get_property)(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32* p_value);
    int32 (*mac_set_interface_mode)(uint8 lchip, uint16 lport, ctc_port_if_mode_t* if_mode);
    int32 (*mac_get_link_up)(uint8 lchip, uint16 lport, uint32* p_is_up, uint32 is_port);
    int32 (*mac_get_capability)(uint8 lchip, uint16 lport, ctc_port_capability_type_t type, void* p_value);
    int32 (*mac_set_capability)(uint8 lchip, uint16 lport, ctc_port_capability_type_t type, uint32 value);
    int32 (*serdes_set_property)(uint8 lchip, ctc_chip_property_t chip_prop, void* p_value);
    int32 (*serdes_get_property)(uint8 lchip, ctc_chip_property_t chip_prop, void* p_value);
    int32 (*serdes_set_mode)(uint8 lchip, ctc_chip_serdes_info_t* p_serdes_info);
    int32 (*serdes_set_link_training_en)(uint8 lchip, uint16 serdes_id, uint8 enable);
    int32 (*serdes_get_link_training_status)(uint8 lchip, uint16 serdes_id, uint16* p_value);
    int32 (*datapath_init)(uint8 lchip, ctc_datapath_global_cfg_t* p_datapath_cfg);
    int32 (*mac_init)(uint8 lchip);
    int32 (*mcu_show_debug_info)(uint8 lchip, uint8 mcu_id);
    int32 (*mac_self_checking)(uint8 lchip, uint16 lport);
    int32 (*mac_link_up_event)(uint8 lchip, uint16 lport);
    int32 (*mac_link_down_event)(uint8 lchip, uint16 lport);
    int32 (*datapath_show_xpipe)(uint8 lchip);
    int32 (*datapath_get_extport_start_id)(uint8 lchip, uint16* p_lport_start);
    int32 (*set_other_misc_chan)(uint8 lchip, uint16 lport, uint8 port_type, uint8 speed_mode, uint8 dir_bmp);
    int32 (*cpumac_get_lport_info_by_inner_idx)(uint8 lchip, uint8 inner_idx, uint16* lport, uint8 *is_network);
    int32 (*mac_set_direction_property)(uint8 lchip, uint16 lport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32 value);
    int32 (*mac_get_direction_property)(uint8 lchip, uint16 lport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32* p_value);
    int32 (*mac_set_link_info)(uint8 lchip, uint16 lport, void* p_value);
    int32 (*mac_get_link_info)(uint8 lchip, uint16 lport, void* p_value);
    int32 (*check_datapath_credit_clear)(uint8 lchip, uint32 mac_id, uint32 chan_id);
    int32 (*get_internal_chan_start)(uint8 lchip, uint8 dp_id, uint16* p_chan_id);
    int32 (*dmps_db_port_init)(uint8 lchip, void* p_global_cfg);
    int32 (*anlt_sm_set_fec)(uint8 lchip, uint16 dport, uint32 value);
    int32 (*anlt_sm_get_mcu_id_by_dport)(uint8 lchip, uint16 dport, uint8* p_mcu_id);
    int32 (*mac_set_mac_en)(uint8 lchip, uint16 lport, void* p_port_info, uint8 enable, uint8 db_upt_flag);
    int32 (*mac_set_fec)(uint8 lchip, uint16 lport, void* p_port_info, uint8 fec_val);
    int32 (*mac_set_cl37_mode)(uint8 lchip, uint16 lport, uint32 value);
    int32 (*mac_set_speed)(uint8 lchip, uint16 lport, uint8 speed_mode);
    int32 (*mac_set_xpipe_en)(uint8 lchip, uint16 lport, uint32 value, uint8 dir_bmp);
    int32 (*mac_set_internal_property)(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32 value);
    int32 (*mac_get_internal_property)(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, uint32* p_value);
    int32 (*mac_dynamic_switch_set_config)(uint8 lchip, void* p_ds_list, uint32 option_bmp);
    int32 (*mac_dynamic_switch_get_list)(uint8 lchip, uint16 lport, void* p_mode, void* p_ds_list);
    int32 (*mac_dynamic_switch_serdes_get_list)(uint8 lchip, void* p_serdes_info, void* p_ds_list);
    int32 (*mac_get_sfd_en)(uint8 lchip, uint16 lport, uint32 *enable);
    int32 (*mac_set_sfd_en)(uint8 lchip, uint16 lport, uint32 enable);
    int32 (*mac_set_cl37_en)(uint8 lchip, uint16 lport, uint32 enable);
    int32 (*mac_set_cl73_en)(uint8 lchip, uint16 lport, uint32 enable, uint8 restart);
    int32 (*mac_get_cl37_en)(uint8 lchip, uint16 lport, uint32* p_en);
    int32 (*mac_get_cl37_mode)(uint8 lchip, uint16 lport, uint32* p_mode);
    int32 (*mac_isr_event_dispatch)(uint8 lchip, uint32 intr, void* p_data, uint8* p_link_intr, ctc_port_link_status_t* port_link_status);
    int32 (*cpumac_isr_event_dispatch)(uint8 lchip, uint32 intr, void* p_data, uint8* p_link_intr, ctc_port_link_status_t* port_link_status);
    int32 (*mac_dynamic_switch_set_group_power)(uint8 lchip, sys_dmps_ds_list_t* p_list, uint8 dyn_flag);
    int32 (*serdes_to_psd)(uint8 lchip, uint16 serdes_id, uint16* psd);
    int32 (*psd_to_serdes)(uint8 lchip, uint16 psd, uint16* serdes_id);
    int32 (*mcu_get_mac_stats)(uint8 lchip, uint32 block_id, sys_usw_dmps_mac_stats_t* p_mac_stats);
    int32 (*mcu_clear_mac_stats)(uint8 lchip, uint32 block_id, uint8 dir);
    int32 (*serdes_get_fw_version)(uint8 lchip, void* p_value);
    int32 (*mac_set_err_inject)(uint8 lchip, uint16 lport, void* p_value);
    int32 (*mac_get_err_inject)(uint8 lchip, uint16 lport, void* p_value);
    int32 (*mac_daemon_thread)(uint8 lchip, uint16 lport);
    int32 (*mac_set_rx_pmac_sfd_en)(uint8 lchip, uint16 lport, uint32 enable);
    int32 (*mac_set_tx_pmac_sfd_en)(uint8 lchip, uint16 lport, uint32 enable);
    int32 (*set_cl73_ability_ext)(uint8 lchip, uint16 lport, uint32 value);
    int32 (*mcu_get_version)(uint8 lchip, sys_usw_dmps_mcu_fw_version_t* p_mcu_version);
    int32 (*mcu_hw_lock)(uint8 lchip, uint8 core_id, uint32 core_mcu_id, uint8 grand_id, uint8 bit);
    int32 (*mcu_hw_unlock)(uint8 lchip, uint8 core_id, uint32 core_mcu_id, uint8 grand_id, uint32 bit);
    int32 (*mac_set_port_cl73_ability)(uint8 lchip, uint16 lport, void* p_ability);
    int32 (*mac_get_cl37_an_remote_status)(uint8 lchip, uint16 lport, uint32 auto_neg_mode, uint32* p_speed, uint32* p_link);
    int32 (*serdes_get_loopback_en)(uint8 lchip, void* p_data);
    int32 (*mac_get_self_check_info)(uint8 lchip, uint16  lport, void* p_self_check_info);
    int32 (*mac_isr_m2c_handler)(uint8 lchip, uint8 inst_id);
    int32 (*serdes_download_firmware)(uint8 lchip, uint16 serdes_id, uint8 flag);
};
typedef struct sys_usw_mchip_dmps_s sys_usw_mchip_dmps_t;

/*SerDes*/
struct sys_usw_mchip_serdes_s
{
    int32 (*serdes_set_group_init)(uint8 lchip, uint16 grp);
    int32 (*serdes_set_lane_init)(uint8 lchip, uint16 serdes);
    int32 (*serdes_set_lane_speed)(uint8 lchip, uint16 serdes, uint8 dir, uint8 spd);
    int32 (*serdes_set_group_speed)(uint8 lchip, uint16 grp, uint8 grp_spd);
    int32 (*serdes_set_lane_fw_load)(uint8 lchip, uint16 serdes, void* p_fw);
    int32 (*serdes_set_group_fw_load)(uint8 lchip, uint16 grp, void* p_fw);
    int32 (*serdes_set_lane_power)(uint8 lchip, uint16 serdes, uint8 dir, uint8 pw_up);
    int32 (*serdes_set_group_power)(uint8 lchip, uint16 grp, uint8 pw_up);
    int32 (*serdes_set_lane_en)(uint8 lchip, uint16 serdes, uint8 dir, uint8 en);
    int32 (*serdes_set_lane_rst)(uint8 lchip, uint16 serdes, uint8 dir, uint8 rst_level, uint8 rst_val);
    int32 (*serdes_set_rx_force_sigdet)(uint8 lchip, uint16 serdes, uint8 fc_up);
    int32 (*serdes_set_rx_sigdet_thrd)(uint8 lchip, uint16 serdes, uint8 thrd_mv);
    int32 (*serdes_set_tx_eq_force)(uint8 lchip, uint16 serdes, void* p_ffe);
    int32 (*serdes_set_lane_prbs_test_pattern)(uint8 lchip, uint16 serdes, uint8 dir, uint8 pattern);
    int32 (*serdes_set_lane_prbs_test_en)(uint8 lchip, uint16 serdes, uint8 dir, uint8 en);
    int32 (*serdes_set_lane_prbs_test_rst)(uint8 lchip, uint16 serdes);
    int32 (*serdes_set_lane_prbs_test_run)(uint8 lchip, uint16 serdes, uint32 duration_ms, void* p_prbs);
    int32 (*serdes_set_rx_ctle_force)(uint8 lchip, uint16 serdes, void* p_ctle);
    int32 (*serdes_set_rx_dfe_force)(uint8 lchip, uint16 serdes, uint32* dfe);
    int32 (*serdes_set_rx_ffe_force)(uint8 lchip, uint16 serdes, uint32* ffe_rx);
    int32 (*serdes_set_rx_ctle_en)(uint8 lchip, uint16 serdes, uint8 en);
    int32 (*serdes_set_rx_dfe_en)(uint8 lchip, uint16 serdes, uint8 en);
    int32 (*serdes_set_rx_ffe_en)(uint8 lchip, uint16 serdes, uint8 en);
    int32 (*serdes_set_lane_loopback)(uint8 lchip, uint16 serdes, void* p_lpbk);
    int32 (*serdes_set_lane_polarity)(uint8 lchip, uint16 serdes, uint8 dir, uint8 pol);
    int32 (*serdes_set_lane_err_inj)(uint8 lchip, uint16 serdes, uint8 err_num);
    int32 (*serdes_set_rx_train_en)(uint8 lchip, uint16 serdes, uint8 en);
    int32 (*serdes_set_tx_train_en)(uint8 lchip, uint16 serdes, uint8 en);
    int32 (*serdes_set_rx_cdr_det_en)(uint8 lchip, uint16 serdes, uint8 en);
    int32 (*serdes_set_lane_precode)(uint8 lchip, uint16 serdes, uint8 dir, uint8 en);
    int32 (*serdes_set_lane_graycode)(uint8 lchip, uint16 serdes, uint8 dir, uint8 en);
    int32 (*serdes_set_lane_msblsb)(uint8 lchip, uint16 serdes, uint8 dir, uint8 value);
    int32 (*serdes_set_group_reg)(uint8 lchip, uint16 grp, uint32 addr, uint32 mask, uint32 data);
    int32 (*serdes_set_lane_reg)(uint8 lchip, uint16 serdes, uint32 addr, uint32 mask, uint32 data);
    int32 (*serdes_set_fw_cmd)(uint8 lchip, uint16 fw_id, void* fw_cmd);
    int32 (*serdes_get_lane_speed)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_spd);
    int32 (*serdes_get_lane_fw_version)(uint8 lchip, uint16 serdes, void* p_fw_ver);
    int32 (*serdes_get_group_fw_version)(uint8 lchip, uint16 grp, void* p_fw_ver);
    int32 (*serdes_get_lane_fw_stat)(uint8 lchip, uint16 serdes, uint8* p_stat);
    int32 (*serdes_get_group_fw_stat)(uint8 lchip, uint16 serdes, uint8* p_stat);
    int32 (*serdes_get_group_pll_lock)(uint8 lchip, uint16 serdes, uint8* p_pll_lock);
    int32 (*serdes_get_lane_pll_lock)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_pll_lock);
    int32 (*serdes_get_rx_sigdet)(uint8 lchip, uint16 serdes, uint8* p_sig_det);
    int32 (*serdes_get_rx_sigdet_thrd)(uint8 lchip, uint16 serdes, uint32* p_thrd_mv);
    int32 (*serdes_get_rx_force_sigdet)(uint8 lchip, uint16 serdes, uint8* p_is_fc, uint8* p_sigdet);
    int32 (*serdes_get_rx_ready)(uint8 lchip, uint16 serdes, uint8* p_rdy);
    int32 (*serdes_get_lane_en)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_en);
    int32 (*serdes_get_lane_rst)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_rst);
    int32 (*serdes_get_tx_eq)(uint8 lchip, uint16 serdes, void* p_ffe);
    int32 (*serdes_get_lane_prbs_test_pattern)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_pattern);
    int32 (*serdes_get_lane_prbs_test_en)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_en);
    int32 (*serdes_get_lane_prbs_test_cnt)(uint8 lchip, uint16 serdes, void *p_prbs);
    int32 (*serdes_get_rx_ctle)(uint8 lchip, uint16 serdes, void* p_ctle);
    int32 (*serdes_get_rx_dfe)(uint8 lchip, uint16 serdes, uint32* dfe);
    int32 (*serdes_get_rx_ffe)(uint8 lchip, uint16 serdes, uint32* ffe_rx);
    int32 (*serdes_get_rx_ctle_en)(uint8 lchip, uint16 serdes, uint8* p_en);
    int32 (*serdes_get_rx_dfe_en)(uint8 lchip, uint16 serdes, uint8* p_en);
    int32 (*serdes_get_rx_ffe_en)(uint8 lchip, uint16 serdes, uint8* p_en);
    int32 (*serdes_get_lane_loopback)(uint8 lchip, uint16 serdes, void* p_lpbk);
    int32 (*serdes_get_lane_polarity)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_pol);
    int32 (*serdes_get_lane_power)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_pw_up);
    int32 (*serdes_get_group_power)(uint8 lchip, uint16 serdes, uint8* p_pw_up);
    int32 (*serdes_get_rx_train_stat)(uint8 lchip, uint16 serdes, uint8* p_en, uint8* p_stat, uint32* p_reason);
    int32 (*serdes_get_tx_train_stat)(uint8 lchip, uint16 serdes, uint8* p_en, uint8* p_stat, uint32* p_reason);
    int32 (*serdes_get_rx_eye_open)(uint8 lchip, uint16 serdes, uint8 wh_sel, uint32* p_eo_margin);
    int32 (*serdes_get_rx_eye_plot)(uint8 lchip, uint16 serdes, uint32* p_eye_data);
    int32 (*serdes_get_rx_cdr_det_en)(uint8 lchip, uint16 serdes, uint8* p_en);
    int32 (*serdes_get_rx_cdr_lock)(uint8 lchip, uint16 serdes, uint8* p_is_lock);
    int32 (*serdes_get_rx_snr)(uint8 lchip, uint16 serdes, uint32* p_snr_db);
    int32 (*serdes_get_lane_reg)(uint8 lchip, uint16 serdes, uint32 addr, uint32 mask, uint32* p_data);
    int32 (*serdes_get_group_reg)(uint8 lchip, uint16 grp, uint32 addr, uint32 mask, uint32* p_data);
    int32 (*serdes_dbg_info)(uint8 lchip, uint16 serdes, uint32 dbg_in, uint32* dbg_out);
    int32 (*serdes_get_lane_precode)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_en);
    int32 (*serdes_get_lane_graycode)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_en);
    int32 (*serdes_get_lane_msblsb)(uint8 lchip, uint16 serdes, uint8 dir, uint8* p_value);
    int32 (*serdes_set_rx_optical_mode)(uint8 lchip, uint16 serdes, uint8 en);
    int32 (*serdes_get_rx_optical_mode)(uint8 lchip, uint16 serdes, uint8* p_en);
    int32 (*serdes_get_lane_port_info)(uint8 lchip, uint16 serdes, void* p_lane_port);
    int32 (*serdes_dump)(uint8 lchip, uint16 serdes);
};
typedef struct sys_usw_mchip_serdes_s sys_usw_mchip_serdes_t;

/*FLEXE*/
struct sys_usw_mchip_flexe_s
{
    int32 (*flexe_set_en)(uint8 lchip, uint16 serdes_id, uint8 enable);
    int32 (*flexe_get_en)(uint8 lchip, uint16 serdes_id, uint8* enable);
    int32 (*flexe_create_group)(uint8 lchip, uint32 group_id, ctc_flexe_grp_t* p_group);
    int32 (*flexe_destroy_group)(uint8 lchip, uint32 group_id);
    int32 (*flexe_get_group)(uint8 lchip, uint32 group_id, ctc_flexe_grp_t* p_group);
    int32 (*flexe_set_group_prop)(uint8 lchip, uint32 group_id, ctc_flexe_grp_prop_t group_prop, void* p_value);
    int32 (*flexe_get_group_prop)(uint8 lchip, uint32 group_id, ctc_flexe_grp_prop_t group_prop, void* p_value);
    int32 (*flexe_add_client)(uint8 lchip, uint32  client_id, ctc_flexe_client_t* p_client);
    int32 (*flexe_remove_client)(uint8 lchip, uint32  client_id);
    int32 (*flexe_get_client)(uint8 lchip, uint32  client_id, ctc_flexe_client_t* p_client);
    int32 (*flexe_set_client_prop)(uint8 lchip, uint32  client_id, uint32 client_prop, void* p_value);
    int32 (*flexe_get_client_prop)(uint8 lchip, uint32  client_id, uint32 client_prop, void* p_value);
    int32 (*flexe_get_client_link_up)(uint8 lchip, uint32  client_id, uint8* p_is_up);
    int32 (*flexe_set_client_cross)(uint8 lchip, ctc_flexe_cross_t* p_cross);
    int32 (*flexe_get_client_cross)(uint8 lchip, ctc_flexe_cross_t* p_cross);
    int32 (*flexe_set_phy_prop)(uint8 lchip, uint16 serdes_id, ctc_flexe_phy_prop_t phy_prop, void* p_value);
    int32 (*flexe_get_phy_prop)(uint8 lchip, uint16 serdes_id, ctc_flexe_phy_prop_t phy_prop, void* p_value);
    int32 (*flexe_get_phy_inst_id)(uint8 lchip, uint8 dp_id, uint8 asic_inst_id, uint8* p_serdes_id, uint32* p_instance_id);
    int32 (*flexe_get_phy_oh_sync)(uint8 lchip, uint8 serdes_id, uint32* p_enable);
    int32 (*flexe_get_dp_asic_id)(uint8 lchip, uint8 serdes_id, uint32 instance_id, uint8* p_dp_id, uint8 p_asic_inst_id[]);
    int32 (*flexe_init)(uint8 lchip, void* p_cfg);
    int32 (*flexe_deinit)(uint8 lchip);
    int32 (*flexe_monitor)(uint8 lchip);
    int32 (*flexe_monitor_cr_timer)(uint8 lchip);
    int32 (*flexe_event_isr)(uint8 lchip, uint32 intr, void* p_data);
    int32 (*flexe_update_misc)(uint8 lchip);
    int32 (*flexe_debug_show_ins_sch)(uint8 lchip, uint8 flexe_shim_id, uint8 inst_id, uint8 dir);
    int32 (*flexe_debug_show_inst_status)(uint8 lchip, uint8 flexe_shim_id);
    int32 (*flexe_debug_show_inst_ohram)(uint8 lchip, uint8 flexe_shim_id, uint8 inst_id, uint8 dir);
    int32 (*flexe_debug_show_client)(uint8 lchip, uint32 client_id);
    int32 (*flexe_debug_show_group)(uint8 lchip, uint32 group_id);
    int32 (*flexe_debug_show_status)(uint8 lchip);
    int32 (*flexe_debug_show_alarm)(uint8 lchip);
    int32 (*flexe_wb_restore_sch)(uint8 lchip, void* group_node);
    int32 (*flexe_monitor_alarm)(uint8 lchip);
};
typedef struct sys_usw_mchip_flexe_s sys_usw_mchip_flexe_t;

/*Ipuc*/
struct sys_usw_mchip_ipuc_s
{
    int32 (*tcam_init)(uint8 lchip, uint8 route_mode, void* ofb_cb_fn);
    int32 (*tcam_deinit)(uint8 lchip, uint8 route_mode);
    int32 (*tcam_get_blockid)(uint8 lchip, void *p_data, uint8 *block_id);
    int32 (*tcam_write_key)(uint8 lchip, void *p_data);
    int32 (*tcam_write_ad)(uint8 lchip, void *p_data);
    int32 (*tcam_move)(uint8 lchip, uint32 new_index, uint32 old_index, void *p_ofb_cb);
    int32 (*show_tcam_key)(uint8 lchip, void *p_data);
    int32 (*show_tcam_status)(uint8 lchip, sal_file_t p_f);
    int32 (*show_sram_usage)(uint8 lchip);
    int32 (*alpm_init)(uint8 lchip, ctc_ipuc_global_cfg_t* p_ipuc_global_cfg, uint8 ipsa_enable);
    int32 (*alpm_deinit)(uint8 lchip);
    int32 (*alpm_add)(uint8 lchip, void* p_ipuc_param, uint32 ad_index, void *wb_alpm_info);
    int32 (*alpm_del)(uint8 lchip, void* p_ipuc_param);
    int32 (*alpm_update)(uint8 lchip, void* p_ipuc_param, uint32 ad_index);
    int32 (*alpm_arrange_fragment)(uint8 lchip, void *p_info_list);
    int32 (*alpm_show_alpm_key)(uint8 lchip, void* p_ipuc_param);
    int32 (*alpm_show_status)(uint8 lchip);
    int32 (*alpm_mapping_wb_master)(uint8 lchip, uint8 sync);
    int32 (*alpm_get_wb_info)(uint8 lchip, void* p_ipuc_param, void* p_alpm_info);
    int32 (*alpm_dump_db)(uint8 lchip, sal_file_t p_f, ctc_global_dump_db_t* p_dump_param);
    int32 (*alpm_merge)(uint8 lchip, uint32 vrf_id, uint8 ip_ver);
    int32 (*alpm_set_fragment_status)(uint8 lchip, uint8 ip_ver, uint8 status);
    int32 (*alpm_get_fragment_status)(uint8 lchip, uint8 ip_ver, uint8* status);
    int32 (*alpm_get_fragment_auto_enable)(uint8 lchip, uint8* enable);
    int32 (*alpm_get_real_tcam_index)(uint8 lchip, uint16 soft_tcam_index, uint8 *real_lchip, uint16* real_tcam_index);
    int32 (*alpm_check_route_info)(uint8 lchip, void *info, void* cb);
    int32 (*alpm_move_sram)(uint8 lchip, uint8 old_lchip, uint8 new_lchip, uint16 old_index, uint16 new_index, void* p_temp_tcam_item, void* ad);
    int32 (*alpm_wb_prefix_restore)(uint8 lchip);
    int32 (*alpm_wb_prefix_sync)(uint8 lchip, uint32 app_id, void *p_wb_data);
    int32 (*alloc_tcam_key_index)(uint8 lchip, void *p_data);
    int32 (*free_tcam_key_index)(uint8 lchip, void *p_data);
    int32 (*tcam_move_cb)(uint8 lchip, uint32 new_index, uint32 old_index, void *pdata);
    int32 (*build_ipda_nexthop)(uint8 lchip, void* p_v_sys_param, void* temp_dsnh_info, void* p_v_dsipda);
    int32 (*write_ipda)(uint8 lchip, void* p_v_sys_param, uint8 by_user, void* p_v_nhinfo);
    int32 (*alpm_wb_set_tcam_index)(uint8 lchip);
    int32 (*alpm_wb_set_ad_info)(uint8 lchip);
    /* nalpm2 */
    int32 (*nalpm2_init)(uint8 lchip, ctc_ipuc_global_cfg_t* p_ipuc_global_cfg, uint8 ipsa_enable);
    int32 (*nalpm2_deinit)(uint8 lchip);
    int32 (*nalpm2_add)(uint8 lchip, void* p_sys_ipuc_param_v, uint32 ad_index, void* data);
    int32 (*nalpm2_del)(uint8 lchip, void* p_sys_ipuc_param_v, void *p_lkp_rlt_inner);
    int32 (*nalpm2_update)(uint8 lchip, void* p_sys_ipuc_param_v, uint32 ad_index);
    int32 (*nalpm2_show_sram_usage)(uint8 lchip);
    int32 (*nalpm2_show_route_info)(uint8 lchip, void* p_ipuc_param_v);
    int32 (*nalpm2_show_status)(uint8 lchip);
    int32 (*nalpm2_dump_db)(uint8 lchip, sal_file_t p_f, ctc_global_dump_db_t* p_dump_param);
    int32 (*nalpm2_check_route)(uint8 lchip, void *p_info, void* cb);
    int32 (*nalpm2_wb_prefix_sync)(uint8 lchip, uint32 app_id, void *p_temp_wb_data);
    int32 (*nalpm2_wb_prefix_restore)(uint8 lchip);
    int32 (*nalpm2_wb_get_info)(uint8 lchip, void* p_ipuc_param_v, void* p_alpm_info);
    int32 (*nalpm2_wb_set_tcam_index)(uint8 lchip);
    int32 (*nalpm2_wb_set_ad_info)(uint8 lchip);
};
typedef struct sys_usw_mchip_ipuc_s sys_usw_mchip_ipuc_t;
/*ACL*/
struct sys_usw_mchip_acl_s
{
    int32 (*init)(uint8 lchip);
    void  (*deinit)(uint8 lchip);
    int32 (*set_flex_key_fields)(uint8 lchip, ctc_acl_flex_key_t* acl_flex_key);
    int32 (*get_flex_key_fields)(uint8 lchip, ctc_acl_flex_key_t* acl_flex_key);
    int32 (*create_presel)(uint8 lchip, ctc_acl_presel_t* acl_presel);
    int32 (*destroy_presel)(uint8 lchip, uint16 presel_id);
    int32 (*add_presel_fields)(uint8 lchip, uint16 presel_id, uint8 fields_cnt, ctc_field_key_t *fields);
    int32 (*remove_presel_fields)(uint8 lchip, uint16 presel_id, uint8 fields_cnt, ctc_field_key_t *fields);
    int32 (*alloc_tcam_entry)(uint8 lchip, void* pg, void* pe);
    int32 (*free_tcam_entry)(uint8 lchip, void* pg, void* pe);
    int32 (*build_key_field)(uint8 lchip,  ctc_field_key_t* pKey, void* pe,  uint8 is_add);
    int32 (*get_key_field)(uint8 lchip, void* pe, ctc_field_key_t* pKey, uint32* key_width);
    int32 (*show_key_field)(uint8 lchip, void* pe, uint8 show_inner);
    int32 (*show_flex_hash_field)(uint8 lchip, void* pe);
    int32 (*add_egs_action_field)(uint8 lchip, ctc_acl_field_action_t* action_field, void* pe_info, uint8 is_add);
    int32 (*get_egs_action_field)(uint8 lchip, ctc_acl_field_action_t* action_field, void* pe_info);
    int32 (*set_league_mode_flex)(uint8 lchip, ctc_acl_league_t* league, uint8* p_sub_blk_cnt, uint8* sub_blk, uint8* p_op_mode);
    int32 (*expand_link_block)(uint8 lchip, void* pb, void* fk, uint8 part_num);
    int32 (*compress_link_block)(uint8 lchip, void* pb, void* fk);
    uint8 (*get_league_update_flag)(uint8 lchip, uint8 dir, uint8 is_port, uint8 is_vlan, uint8 is_l3if);
    int32 (*add_compress_ether_type)(uint8 lchip, uint8 is_global, uint8 dir, uint16 new_ether_type, uint16 old_ether_type,uint8* o_cether_type, uint8* o_cether_type_index);
    int32 (*remove_compress_ether_type)(uint8 lchip, uint8 is_global, uint8 dir, uint16 ether_type);
    int32 (*add_udf_entry)(uint8 lchip,  ctc_acl_classify_udf_t* p_udf_entry);
    int32 (*show_flex_keygen)(uint8 lchip, uint8 dir, uint8 key_type, uint32 eid, uint32* data);
    void* (*get_flex_key)(uint8 lchip, uint8 dir, uint8 key_type);
    int32 (*wb_sync)(uint8 lchip, uint32 app_id, void* p_wb_data, void* p_user_data);
    int32 (*wb_restore)(uint8 lchip, void* p_wb_query);
    int32 (*set_league_global_config)(uint8 lchip, void* config);
    int32 (*reorder_entry)(uint8 lchip, ctc_acl_reorder_t* reorder);
    void  (*show_kset)(uint8 lchip, ctc_acl_flex_key_t *acl_flex_key);
    int32 (*add_hash_nsh_sel_field)(uint8 lchip, uint8 field_sel_id, ctc_field_key_t* sel_field, uint8 is_add);
    int32 (*add_flex_hash_field)(uint8 lchip, ctc_field_key_t* pKey, void* pe, uint8 is_add);
    int32 (*replace_block)(uint8 lchip, ctc_acl_replace_t* replace);
    int32 (*enable_udf_ipfix)(uint8 lchip, uint16 udf_hit_idx,uint8 enable);
};
typedef struct sys_usw_mchip_acl_s sys_usw_mchip_acl_t;
struct sys_usw_mchip_scl_s
{
    int32 (*build_hash_key_svlan_dscp_port)(uint8 lchip, ctc_field_key_t* pKey, void* pe, uint8 is_add);
    int32 (*build_field_action_igs_vlan_edit)(uint8 lchip, void* ds, void* pe, ctc_scl_field_action_t* pAction, uint8 is_add);
    int32 (*build_field_action_igs)(uint8 lchip, ctc_scl_field_action_t* pAction, void* pe, uint8 is_add);
    int32 (*build_field_action_flow)(uint8 lchip, ctc_scl_field_action_t* pAction, void* pe, uint8 is_add);
    int32 (*get_field_action_igs)(uint8 lchip, ctc_scl_field_action_t* p_action, void* pe);
    int32 (*get_field_action_flow)(uint8 lchip, ctc_scl_field_action_t* pAction, void* pe);
    int32 (*update_action)(uint8 lchip, void* data, void* change_nh_param);
    int32 (*get_userid_default_action)(uint8 lchip, void* p_default_action);
    int32 (*add_compress_ether_type)(uint8 lchip, uint16 new_ether_type, uint16 old_ether_type,uint8* o_cether_type, uint8* o_cether_type_index);
    int32 (*remove_compress_ether_type)(uint8 lchip, uint8 ether_type_index);
    int32 (*move_dsuserid_to_temp)(uint8 lchip, void* ds, uint8 userid_bmp);
    int32 (*scl_set_flex_key)(uint8 lchip, void* scl_flex_key, uint8 inner);
    int32 (*scl_build_flex_key_field)(uint8 lchip, void * pKey_info, void * pe_info, uint8 is_add);
    int32 (*scl_get_flex_key)(uint8 lchip, void* scl_flex_key, uint8 inner);
    int32 (*show_flex_key)(uint8 lchip, void* data, uint32* key_id, uint32* ad_id);
    int32 (*set_xkey_valid)(uint8 lchip, void * user_data, uint8 is_add);
    int32 (*build_hash_key_nsh)(uint8 lchip, ctc_field_key_t* pKey, void* pe, uint8 is_add);
    int32 (*entry_pp_hash_init)(uint8 lchip);
    int32 (*entry_pp_hash_deinit)(uint8 lchip);
    int32 (*scl_get_flex_key_sets)(uint8 lchip, void * scl_flex_key);
};
typedef struct sys_usw_mchip_scl_s sys_usw_mchip_scl_t;

/*L3IF*/
struct sys_usw_mchip_l3if_s
{
    int32 (*set_router_mac)(uint8 lchip, uint16 l3if_id, ctc_l3if_router_mac_t router_mac);
    int32 (*set_system_router_mac)(uint8 lchip, mac_addr_t mac_addr);
    int32 (*db_init)(uint8 lchip, uint8 deinit);
    int32 (*wb_rtmac_restore)(uint8 lchip);
    int32 (*add_router_mac_entry)(uint8 lchip, uint32 entry_id, ctc_l3if_rmac_entry_t* rmac_entry);
    int32 (*remove_router_mac_entry)(uint8 lchip, uint32 entry_id);
    int32 (*get_router_mac_entry)(uint8 lchip, uint32 entry_id, ctc_l3if_rmac_entry_t* rmac_entry);
    int32 (*show_router_mac_entry)(uint8 lchip, uint32 entry_id);
    int32 (*wb_rtmac_sync)(uint8 lchip,uint32 app_id);
    int32 (*dump_db)(uint8 lchip, sal_file_t p_f,ctc_global_dump_db_t* p_dump_param);
    int32 (*get_router_mac)(uint8 lchip, uint16 l3if_id, ctc_l3if_router_mac_t* router_mac);
};
typedef struct sys_usw_mchip_l3if_s sys_usw_mchip_l3if_t;
/*IPFIX*/
struct sys_usw_mchip_ipfix_s
{
    int32 (*decode_key_ad)(uint8 lchip, void* p_data, uint8 is_ad, void* p_key);
    int32 (*encode_ad)(uint8 lchip, void* p_key);
    int32 (*set_prop_cfg)(uint8 lchip, void* cfg);
    int32 (*get_prop_cfg)(uint8 lchip, void* cfg);
    int32 (*set_global_cfg)(uint8 lchip, void* cfg);
    int32 (*get_global_cfg)(uint8 lchip, void* cfg);
    int32 (*set_flow_cfg)(uint8 lchip, void* cfg);
    int32 (*get_flow_cfg)(uint8 lchip, void* cfg);
    int32 (*init_register)(uint8 lchip, void* p_global_cfg);
    int32 (*sync_data)(uint8 lchip, void* p_dma_info);
    int32 (*traverse_dma)(uint8 lchip, void* fn, void* p_data, uint8 is_remove);
    int32 (*cb_init)(uint8 lchip);
    int32 (*ipfix_set_flex_key)(uint8 lchip, void* ipfix_flex_key);
    int32 (*ipfix_get_flex_key)(uint8 lchip, void* ipfix_flex_key);
    int32 (*ipfix_get_flex_key_sets)(uint8 lchip, void* ipfix_flex_key);
    int32 (*ipfix_encode_xkey_hash)(uint8 lchip, void* param);
};
typedef struct sys_usw_mchip_ipfix_s sys_usw_mchip_ipfix_t;
/* Learning & Aging */
struct sys_usw_mchip_aging_s
{
    int32 (*set_register)(uint8 lchip);
    int32 (*get_key_index)(uint8 lchip, uint32 aging_ptr, uint8* domain_type, uint32* key_index);
    int32 (*get_aging_ptr)(uint8 lchip, uint8 domain_type, uint32 key_index, uint32* aging_ptr);
    int32 (*set_aging_status)(uint8 lchip, uint8 domain_type, uint32 key_index, uint8 timer, uint8 status);
    int32 (*get_aging_status)(uint8 lchip, uint8 domain_type, uint32 key_index, uint8* hit);
    int32 (*get_aging_timer)(uint8 lchip, uint8 domain_type, uint32 key_index, uint8* p_timer);
    int32 (*aging_init)(uint8 lchip);
};
typedef struct sys_usw_mchip_aging_s sys_usw_mchip_aging_t;
/*Nexthop*/
struct sys_usw_mchip_nh_s
{
    int32 (*fp_init)(uint8 lchip);
    int32 (*add_fp)(uint8 lchip, void* p_fp_edit, uint8 is_internal);
    int32 (*remove_fp)(uint8 lchip, uint32 fp_id);
    int32 (*update_fp)(uint8 lchip, void* p_fp_edit);
    int32 (*get_fp_db)(uint8 lchip, uint32 fp_id, void** pp_nh_fp_db);
    int32 (*get_fp_info)(uint8 lchip, uint32 fp_id, void* p_fp_info);
    int32 (*get_tunnel_info)(uint8 lchip, void* p_nhinfo, char* tunnel_type,char* ipsa, char * ipda, char * gre_key);
    int32 (*get_misc_edit_param)(uint8 lchip, void* p_nhinfo, void* p_param);
    int32 (*add_dsmet_entry)(uint8 lchip, void* p_mem_param, uint32 dsnh_offset, uint8 use_dsnh8w, void* p_db_member_list, void* p_info_mcast);
    void(*dump_mcast_bitmap_info)(uint8 lchip, void* p_meminfo, uint8 gchip, uint32* p_memcnt, void* dsmet);
    int32 (*get_mcast_member_info)(uint8 lchip, void* p_mcast_db, void* p_nh_info);
    int32 (*analyze_member)(uint8 lchip, void* p_db_member_list, void* p_member, void** pp_mem_node, bool* p_entry_exit);
    int32 (*update_mcast_mem)(uint8 lchip, void* p_mem_param, void* p_db_member_list, void* p_info_mcast, void* p_member_info, uint8 is_add);
    int32 (*add_nsh_id)(uint8 lchip, uint16 nsh_id, ctc_nh_nsh_param_t* nsh_info, uint32 stats_ptr, uint8 op_type);
    int32 (*update_nsh_id)(uint8 lchip, uint16 nsh_id, ctc_nh_nsh_param_t* nsh_info, uint32 stats_ptr);
    int32 (*remove_nsh_id)(uint8 lchip, uint16 nsh_id);
    int32 (*get_nsh_edit_info)(uint8 lchip, uint16 nsh_id, void* p_edit);
    int32 (*nsh_init)(uint8 lchip, uint8 is_deinit);
    int32 (*wb_restore)(uint8 lchip, ctc_wb_query_t *p_wb_query);
    int32 (*wb_sync)(uint8 lchip, uint32 app_id, ctc_wb_data_t* p_wb_data);
    int32 (*clear_dlb_flow)(uint8 lchip, void* p_nhdb);
};
typedef struct sys_usw_mchip_nh_s sys_usw_mchip_nh_t;

/*Misc*/
struct sys_usw_mchip_misc_s
{
    int32 (*mchip_cap_init)(uint8 lchip);
    int32 (*mem_bist_set)(uint8 lchip, void* p_val);
    int32 (*map_drop_reason_sys_to_ctc)(uint16 discard_type, uint16* p_drop_reason);
    int32 (*map_discard_type)(uint8 lchip, uint8 dir, uint8 drop_reason_en);
    int32 (*register_get_glb_acl_table)(uint8 lchip, uint8 dir, void* p_glb_acl_lkup);
    void* (*com_entry_hash_init)(uint8 lchip, uint32 entry_num, uint32 block_size);
    int32 (*com_entry_hash_deinit)(uint8 lchip, void* user_data);
    void* (*com_lookup_entry_hash)(void* user_data, uint32 entry_id);
    int32 (*com_add_entry_hash)(uint8 lchip, uint32 mem_mode, void* user_data, uint32 entry_id, uint16 pp_bmp);
    int32 (*com_remove_entry_hash)(uint8 lchip, void* user_data, void* node);
    int32 (*com_remove_entry_hash_by_entry_id)(uint8 lchip, void* user_data, uint32 entry_id);
    int32 (*get_drop_resson_info)(uint16 discard_type, uint8* p_dir, uint8* p_clear_on_read);
};
typedef struct sys_usw_mchip_misc_s sys_usw_mchip_misc_t;
/*Paser*/
struct sys_usw_mchip_paser_s
{

    int32 (*set_hash_field)(uint8 lchip, void* p_hash_ctl, uint8 hash_usage);
    int32 (*get_hash_field)(uint8 lchip, void* p_hash_ctl, uint8 hash_usage);
    int32 (*hash_init)(uint8 lchip);
    int32 (*parser_set_global_cfg)(uint8 lchip, ctc_parser_global_cfg_t* global_cfg);
    int32 (*parser_get_global_cfg)(uint8 lchip, ctc_parser_global_cfg_t* global_cfg);
};
typedef struct sys_usw_mchip_paser_s sys_usw_mchip_paser_t;
struct sys_usw_mchip_hash_s
{
    int32 (*set_cfg)(uint8 lchip, void* p_hash_cfg);
    int32 (*get_cfg)(uint8 lchip, void* p_hash_cfg);
    int32 (*set_offset)(uint8 lchip, void* p_hash_offset);
    int32 (*get_offset)(uint8 lchip, void* p_hash_offset);
    int32 (*set_hash_ctl)(uint8 lchip, void* p_hash_cfg);
    int32 (*get_hash_ctl)(uint8 lchip, void* p_hash_cfg);
    int32 (*hash_init)(uint8 lchip);
    int32 (*set_selector_ext)(uint8 lchip, void* p_hash_selector_ext);
    int32 (*get_selector_ext)(uint8 lchip, void* p_hash_selector_ext);
    int32 (*set_selector_remap)(uint8 lchip, void* p_hash_selector_remap);
    int32 (*get_selector_remap)(uint8 lchip, void* p_hash_selector_remap);
    int32 (*set_mask_profile_en)(uint8 lchip, uint8 sel_grp_id, uint8 enable);
    int32 (*set_udf_hash_en)(uint8 lchip, void* p_hash_poly);
    int32 (*get_udf_hash_en)(uint8 lchip, void* p_hash_poly);
    int32 (*set_field)(uint8 lchip, void* p_hash_fields);
    int32 (*get_field)(uint8 lchip, void* p_hash_fields);
};
typedef struct sys_usw_mchip_hash_s sys_usw_mchip_hash_t;

struct sys_usw_mchip_qos_s
{
    int32 (*qos_policer_alloc_offset)(uint8 lchip, void* p_policer);
    int32 (*qos_policer_free_offset)(uint8 lchip, void* p_policer);
    int32 (*qos_policer_add_to_asic)(uint8 lchip, void* p_policer, void* p_profX,void* p_profY, void* p_action_profile);
    int32 (*qos_policer_remove_from_asic)(uint8 lchip, void* p_policer);
    int32 (*qos_policer_copp_add_to_asic)(uint8 lchip, void* p_policer, void* p_prof);
    int32 (*qos_policer_deinit_opf)(uint8 lchip);
    int32 (*qos_policer_init_opf)(uint8 lchip);
    int32 (*qos_policer_spool_init)(uint8 lchip);
    int32 (*qos_policer_spool_deinit)(uint8 lchip);
    int32 (*qos_policer_init_reg)(uint8 lchip);
    int32 (*qos_policer_copp_init)(uint8 lchip);
    int32 (*qos_policer_restore_offset)(uint8 lchip, void* p_policer);
    int32 (*qos_get_policer_param)(uint8 lchip, void* p_param, void* p_policer);
    int32 (*qos_policer_free_statsptr)(uint8 lchip, void* p_policer, uint32* p_stats_ptr);
    int32 (*qos_shape_add_que_shp_to_asics)(uint8 lchip, uint16 queue_id, uint8 queue_offset, void* p_shape, uint8 is_pps);
    int32 (*qos_shape_add_grp_shp_to_asics)(uint8 lchip, uint32 group_id, uint8 is_pps, uint32 pir, uint32 pbs, uint8 enable);
    int32 (*qos_shape_add_grp_node_shp_to_asics)(uint8 lchip, uint32 group_id, uint8 group_node, uint8 is_pps, uint32 pir, uint32 pbs, uint8 is_cir, uint8 enable);
    int32 (*qos_shape_add_chan_shp_to_asic)(uint8 lchip, uint16 channel, uint32 pir, uint32 pbs, uint8 is_pps, uint8 enable);
    int32 (*qos_shape_get_que_shape_profile)(uint8 lchip, uint16 queue_id, uint16 queue_offset, void* p_shape);
    int32 (*qos_shape_get_grp_shape_profile)(uint8 lchip, uint32 group_id, uint32* rate, uint32* thrd, uint8* pps_en, uint8* p_shp_en);
    int32 (*qos_shape_get_grp_node_shape_profile)(uint8 lchip, uint32 group_id, uint8 group_node, uint8 is_cir, uint32* rate, uint32* thrd, uint8* pps_en, uint8* p_shp_en);
    int32 (*qos_shape_get_port_shape_profile)(uint8 lchip, uint16 channel, uint32* rate, uint32* thrd, uint8* pps_en, uint8* p_shp_en);
    int32 (*qos_shape_set_reason_base_pkt_en)(uint8 lchip, uint8 enable);
    int32 (*qos_queue_write_hash_key)(uint8 lchip, uint32 service_id, uint16 dest_port_or_chan,uint16 group_id,uint8 type, uint8 is_lsp, uint32* p_key_index);
    int32 (*qos_queue_del_hash_key)(uint8 lchip, uint32 key_index);
    int32 (*qos_queue_get_chan_by_grp_id)(uint8 lchip, uint32 group_id, uint16 *channel);
    int32 (*qos_queue_get_chan_by_que_id)(uint8 lchip, uint16 queue_id, uint16 *channel);
    int32 (*qos_queue_get_queue_base)(uint8 lchip, uint8 channel, uint16 queue_offset, uint16* queue_base);
    int32 (*qos_queue_flush)(uint8 lchip,uint16 chan_id,uint16 group_id,uint8 flag, uint16 queue_id);
    int32 (*qos_queue_set_port_drop_en)(uint8 lchip, uint16 chan_id, bool enable);
    int32 (*qos_queue_drop_read_asic)(uint8 lchip, uint8 wred_mode, void* p_queue_node, void* p_sys_profile, uint8* hw_valid);
    int32 (*qos_sch_set_hsched)(uint8 lchip, uint32 gport, uint16 group_id, uint8 enable, uint8 type);
    int32 (*qos_sch_set_queue_sched)(uint8 lchip, uint16 queue_id, uint8 type, uint8 queue_offset, uint8 exceed_class, uint16 exceed_weight);
    int32 (*qos_sch_set_group_sched)(uint8 lchip, void* p_sched_grp);
    int32 (*qos_sch_get_queue_sched)(uint8 lchip, uint16 queue_id, uint8 queue_offset, uint8* exceed_class, uint16* exceed_weight);
    int32 (*qos_sch_get_group_sched)(uint8 lchip, void* p_sched_grp);
    int32 (*qos_sch_create_sched_group)(uint8 lchip, void* p_sched_group, uint32 chan);
    int32 (*qos_sch_destroy_sched_group)(uint8 lchip, void* p_sched_group);
    int32 (*qos_sch_dump_sched_group_child_list)(uint8 lchip, uint32 group_id);
    int32 (*qos_sch_update_fc_group)(uint8 lchip, uint16 chan_id, uint16 ets_group_id, uint8 is_ets, uint8 enable);
    int32 (*qos_resrc_set_que_drop)(uint8 lchip, uint8 is_dynamic, uint8 enable, void* drop_array, void* p_sys_queue);
    int32 (*qos_resrc_fc_get_profile)(uint8 lchip, uint16 chan_id, void* p_fc);
    int32 (*qos_shape_init)(uint8 lchip);
    int32 (*qos_sch_init)(uint8 lchip);
    int32 (*qos_que_init)(uint8 lchip);
    int32 (*qos_fcdl_recover_drop_pkt)(uint8 lchip, void* p_sys_queue_node_param,  uint16 queue_id, uint8  chan_id, uint8 enable, uint8 pfc_en);
    int32 (*qos_api_register)(uint8 lchip, void** api_cb);
    int32 (*qos_fcdl_recover)(uint8 lchip, uint32 gport, uint8 pri_class, uint8 enable);
    int32 (*qos_fcdl_detect_mac)(uint8 lchip, void* p_fcdl, uint8 is_get);
};
typedef struct sys_usw_mchip_qos_s sys_usw_mchip_qos_t;

struct sys_usw_mchip_security_s
{
    int32 (*storm_ctl_get_profile_from_hw)(uint8 lchip, uint32 stmctl_offset,void* p_cfg, void* p_profile_param);
    int32 (*storm_ctl_add_hw)(uint8 lchip, uint32 stmctl_offset, void* p_cfg, void* p_profile_param, uint8 is_add);
};
typedef struct sys_usw_mchip_security_s sys_usw_mchip_security_t;

struct sys_usw_mchip_diag_s
{
    int32 (*get_pkt_trace)(uint8 lchip, void* p_value, uint8 position);
    int32 (*get_drop_info)(uint8 lchip, void* p_value);
    int32 (*set_dbg_pkt)(uint8 lchip, void* p_value);
    int32 (*set_dbg_session)(uint8 lchip, void* p_value);
    int32 (*pkt_trace_clear_rslt)(uint8 lchip, uint32 watch_point);
    int32 (*diag_mem_bist)(uint8 lchip, uint8* err_mem_id);
    int32 (*get_lb_hash)(uint8 lchip, ctc_field_key_t* p_field_list, uint32 field_cnt, ctc_diag_lb_hash_t* p_rslt);
    char* (*get_discard_type_desc)(uint16 discard_type);
    int32 (*diag_get_pos)(uint16 discard, uint8* pos);
    int32 (*map_drop_reason_ctc_to_sys)(uint16 drop_reason, uint32* discard_type_bmp);
    int32 (*diag_get_drop_reason)(uint8 lchip, uint32* reason);
};
typedef struct sys_usw_mchip_diag_s sys_usw_mchip_diag_t;

struct sys_usw_mchip_mon_s
{
    int32 (*set_path_latency)(uint8 lchip, void* p_cfg, uint8 enable);
    int32 (*get_path_latency)(uint8 lchip, void* p_cfg, uint8 *enable);
    int32 (*get_path_latency_watermark)(uint8 lchip, void* p_mon_watermark, uint16 channel_id);
    int32 (*clear_path_latency_watermark)(uint8 lchip, void* p_mon_watermark, uint16 channel_id);
    int32 (*set_global_config)(uint8 lchip, void* p_mon_cfg);
    int32 (*get_global_config)(uint8 lchip, void* p_mon_cfg);
    int32 (*sync_data)(uint8 lchip, void* p_data);
    int32 (*init)(uint8 lchip);
    int32 (*deinit)(uint8 lchip);
    int32 (*show_path)(uint8 lchip);
    int32 (*buf_sync_interval)(uint8 lchip, uint8 is_set, uint32* interval);
    int32 (*buffer_scan)(uint8 lchip, uint8 is_set, void* p_cfg);
    int32 (*op_buffer_watermark)(uint8 lchip, void* p_data, uint8 is_clear);
};
typedef struct sys_usw_mchip_mon_s sys_usw_mchip_mon_t;

struct sys_usw_mchip_flowstats_s
{
    int32 (*stats_type_init)(uint8 lchip);
    int32 (*stats_ram_init)(uint8 lchip);
    int32 (*show_status)(uint8 lchip);
    int32 (*ds2count)(uint8 lchip, uint32 tbl_id, void* p_ds, ctc_stats_basic_t* p_count);
    int32 (*sync_fifo_stats)(uint8 lchip);
    int32 (*set_ram_pp_property)(uint8 lchip, uint8 dir, uint8 block_id, uint32 lkup_level_bitmap, uint8 is_global);
};
typedef struct sys_usw_mchip_flowstats_s sys_usw_mchip_flowstats_t;

struct sys_usw_mchip_macstats_s
{
    int32 (*stats_get_mac_stats)(uint8 lchip, uint32 tbl_id, uint16 tbl_base, uint8 dir, void* p_mac_stats);
    int32 (*stats_clear_mac_stats)(uint8 lchip, uint32 tbl_id, uint16 tbl_base, uint8 dir);
    int32 (*stats_sync_throughput)(uint8 lchip, uint32 lport, uint32 tbl_id, uint16 tbl_base, uint32 mac_ipg);
};
typedef struct sys_usw_mchip_macstats_s sys_usw_mchip_macstats_t;

/*NPM*/
struct sys_usw_mchip_npm_s
{
    int32 (*set_lite_cfg)(uint8 lchip, void* p_cfg);
    int32 (*get_lite_stats)(uint8 lchip, uint32 session_id, void* p_stats);
    int32 (*sync_dma_stats)(uint8 lchip, void* p_data);
    int32(*npm_event_cb)(uint8 gchip, void* p_data);
	int32 (*get_stats_from_asic)(uint8 lchip, void* p_session);
	int32 (*isr_sync_stats)(uint8 lchip, uint32 intr, void* p_data);
};
typedef struct sys_usw_mchip_npm_s sys_usw_mchip_npm_t;

/*Mirror*/
struct sys_usw_mchip_mirror_s
{
    int32 (*mirror_set_dst_to_linkagg)(uint8 lchip, void* met_fifo_excp, uint32* member_list, uint16 member_cnt, uint8 is_set);
    int32 (*mirror_update_linkagg_member)(uint8 lchip, uint16 tid, uint32* member_list, uint16 member_cnt, uint8 is_set);
};
typedef struct sys_usw_mchip_mirror_s sys_usw_mchip_mirror_t;

/* Interrupt */
struct sys_usw_mchip_interrupt_s
{
    int32 (*interrupt_get_sup_info)(uint8 lchip, uint32 intr_type, uint32 *p_sup_table_id, uint16 *p_bit_offset, uint32 *p_func_table_id);
    int32 (*interrupt_get_intrvec_offset)(uint8 lchip, uint32 intr_type, uint32 *p_offset);
    int32 (*interrupt_db_init)(uint8 lchip);
    int32 (*interrupt_dispatch_func)(uint8 lchip, uint32* p_status);
    int32 (*interrupt_dispatch_flexe)(uint8 lchip, uint32 sub_intr);
    int32 (*intrrupt_isr_sup_normal)(uint8 lchip, uint32 intr, void* p_data);
    int32 (*interrupt_init_reg)(uint8 lchip);
    int32 (*interrupt_set_sup_op)(uint8 lchip, uint8 grp_id, uint8 act_idx);
};
typedef struct sys_usw_mchip_interrupt_s sys_usw_mchip_interrupt_t;

/*port*/
struct sys_usw_mchip_port_s
{
    int32 (*port_flow_ctl_init)(uint8 lchip);
    int32 (*port_set_flow_ctl_en)(uint8 lchip, void* p_fc_prop, uint8 is_recover);
    int32 (*port_get_flow_ctl_en)(uint8 lchip, void* p_fc_prop);
    int32 (*port_set_pause_speed)(uint8 lchip, uint32 mac_id, void* p_data);
    int32 (*port_set_property)(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32 value);
    int32 (*port_get_property)(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32* p_value);
    int32 (*port_init)(uint8 lchip);
    int32 (*port_set_min_frame_size)(uint8 lchip, ctc_frame_size_t index, uint16 value);
    int32 (*port_get_min_frame_size)(uint8 lchip, ctc_frame_size_t index, uint16* p_value);
    int32 (*port_set_max_frame_size)(uint8 lchip, ctc_frame_size_t index, uint16 value);
    int32 (*port_get_max_frame_size)(uint8 lchip, ctc_frame_size_t index, uint16* p_value);
    int32 (*port_set_xpipe_en)(uint8 lchip, uint32 gport, uint32 value);
    int32 (*port_set_xpipe_mode)(uint8 lchip, uint32 gport, uint32 value);
};
typedef struct sys_usw_mchip_port_s sys_usw_mchip_port_t;

struct sys_usw_mchip_eunit_s
{
    int32 (*set_cfg)(uint8 lchip, uint8 type, void* p_cfg);
    int32 (*get_cfg)(uint8 lchip, uint8 type, void* p_cfg);
    int32 (*isr_handler)(uint8 lchip, uint32 intr, void* p_data);
    int32 (*reset)(uint8 lchip, uint8 unit, ctc_eunit_install_t* p_eunit);
    int32 (*get_unit)(uint8 lchip, uint8 type, uint8* unit);
    int32 (*get_mcpu_flag)(uint8 lchip, uint32 flag, uint8 mcpu_num,uint8* val);
    int32 (*set_mcpu_flag)(uint8 lchip, uint32 flag, uint8 mcpu_num,uint8 val);
    int32 (*mcpu_read_data)(uint8 lchip, uint8 mcpu_num,uint32* p_data,uint32 lenth);
    int32 (*mcpu_write_data)(uint8 lchip, uint8 mcpu_num,uint32* p_data,uint32 lenth);
    int32 (*load_image)(uint8 lchip, uint8 unit, ctc_eunit_install_t* p_eunit);
    int32 (*show_status)(uint8 lchip, uint8 level, void* p_params);
    int32 (*init_deinit)(uint8 lchip, uint8 is_deinit);
    int32 (*hw_lock)(uint8 lchip, uint8 unit, uint8 lock_id);
    int32 (*hw_unlock)(uint8 lchip, uint8 unit, uint8 lock_id);
    int32 (*get_hw_lock)(uint8 lchip, uint8 type, uint8* eunit_id, uint8* lock_id);
    int32 (*show_dbg_info)(uint8 lchip, uint8 eunit_id);
    int32 (*read_data)(uint8 lchip, uint8 cfg_type, void* p_data,uint16 lenth);
    int32 (*show_dma_stats)(uint8 lchip, uint8 eunit_id);
    int32 (*clear_dma_stats)(uint8 lchip, uint8 eunit_id);
    int32 (*get_pclog)(uint8 lchip, uint8 eunit_id, uint64* pc_arr, uint8* num);
    int32 (*tbl_rw)(uint8 lchip, uint8 eunit_id, void* p_tbl, uint8 is_read);
    int32 (*show_dma_status)(uint8 lchip, uint8 eunit_id);
    int32 (*show_dma_desc)(uint8 lchip, uint8 eunit_id, uint8 chan_id, uint32 start_idx, uint32 end_idx);
    int32 (*show_mem)(uint8 lchip, uint32 addr, uint32 len);
    int32 (*show_io_log)(uint8 lchip, uint8 eunit_id, uint8 clear_en);
    int32 (*mcpu_set_config)(uint8 lchip, uint8 idx, uint32* value);
    int32 (*mcpu_get_config)(uint8 lchip, uint8 idx, uint32* value);
    int32 (*set_run_status)(uint8 lchip, uint8 eunit_id, uint32 run_status);
    int32 (*show_version)(uint8 lchip, uint8 eunit_id);
};
typedef struct sys_usw_mchip_eunit_s sys_usw_mchip_eunit_t;

/*packet*/
struct sys_usw_mchip_packet_s
{
    int32 (*packet_txinfo_to_rawhdr)(uint8 lchip, ctc_pkt_tx_t* p_pkt_tx);
    int32 (*packet_rawhdr_to_rxinfo)(uint8 lchip, uint32* p_raw_hdr_net, ctc_pkt_rx_t* p_pkt_rx);
    int32 (*packet_encap_array)(uint8 lchip, ctc_pkt_tx_t** p_pkt_tx_array, uint32 count);
};
typedef struct sys_usw_mchip_packet_s sys_usw_mchip_packet_t;

/*xdata*/
struct sys_usw_mchip_xdata_s
{
    int32 (*add_fk)(uint8 lchip, void* p_para);
    int32 (*remove_fk)(uint8 lchip, void* p_para);
    int32 (*set_fk_field)(uint8 lchip, void* p_para, uint32* p_ds, uint32 value);
    int32 (*get_fk_field)(uint8 lchip, void* p_para, uint32* p_ds, uint32* value);
    int32 (*prof_get_info)(uint8 lchip, ctc_xdata_t *p_prof, uint8 with_check);
    int32 (*local_get_kset)(uint8 lchip, ctc_xdata_local_type_t type, void* kset);
    int32 (*fk_get_flex_bits)(uint8 lchip, void * p_param);
    int32 (*xdata_init)(uint8 lchip);
    int32 (*xdata_deinit)(uint8 lchip);
    int32 (*set_profile)(uint8 lchip, ctc_xdata_prof_t* p_prof);
    int32 (*get_profile)(uint8 lchip, ctc_xdata_prof_t* p_prof);
    int32 (*set_local)(uint8 lchip, ctc_xdata_local_t* p_local);
    int32 (*get_local)(uint8 lchip, ctc_xdata_local_t* p_local);
    int32 (*set_path)(uint8 lchip, ctc_xdata_path_t* p_path);
    int32 (*get_path)(uint8 lchip, ctc_xdata_path_t* p_path);
    int32 (*func_en)(uint8 lchip, uint32 type, uint8 enable, void* data);
};
typedef struct sys_usw_mchip_xdata_s sys_usw_mchip_xdata_t;

/*oam*/
struct sys_usw_mchip_oam_s
{
    int32 (*get_mep_for_event)(uint8 lchip, void* mep_info);
};
typedef struct sys_usw_mchip_oam_s sys_usw_mchip_oam_t;

/*srv6*/
struct sys_usw_mchip_srv6_s
{
    int32 (*set_gsid_default_action)(uint8 lchip, uint16 lport, uint8 deinit);
};
typedef struct sys_usw_mchip_srv6_s sys_usw_mchip_srv6_t;

/*aps*/
struct sys_usw_mchip_aps_s
{
    int32 (*set_hw)(uint8 lchip, uint16 group_id, void* p_dsaps);
    int32 (*get_hw)(uint8 lchip, uint16 group_id, void* p_dsaps);
    int32 (*set_protections)(uint8 lchip, void* p_grp_bitmap);
};
typedef struct sys_usw_mchip_aps_s sys_usw_mchip_aps_t;

/*PERI*/
struct sys_usw_mchip_peri_s
{
    int32 (*peri_init)(uint8 lchip);
    int32 (*peri_mdio_init)(uint8 lchip);
    int32 (*peri_set_phy_scan_cfg)(uint8 lchip);
    int32 (*peri_set_phy_scan_para)(uint8 lchip, ctc_chip_phy_scan_ctrl_t* p_scan_para);
    int32 (*peri_get_phy_scan_para)(uint8 lchip, ctc_chip_phy_scan_ctrl_t* p_scan_para);
    int32 (*peri_read_phy_reg)(uint8 lchip, ctc_chip_mdio_type_t type, ctc_chip_mdio_para_t* p_para);
    int32 (*peri_write_phy_reg)(uint8 lchip, ctc_chip_mdio_type_t type, ctc_chip_mdio_para_t* p_para);
    int32 (*peri_set_mdio_clock)(uint8 lchip, ctc_chip_mdio_type_t type, uint16 freq);
    int32 (*peri_get_mdio_clock)(uint8 lchip, ctc_chip_mdio_type_t type, uint16* freq);
    int32 (*peri_set_mac_led_mode)(uint8 lchip, ctc_chip_led_para_t* p_led_para, ctc_chip_mac_led_type_t led_type, uint8 inner);
    int32 (*peri_set_mac_led_mapping)(uint8 lchip, ctc_chip_mac_led_mapping_t* p_led_map);
    int32 (*peri_set_mac_led_en)(uint8 lchip, bool enable);
    int32 (*peri_get_mac_led_en)(uint8 lchip, bool* enable);
    int32 (*peri_set_mac_led_clock)(uint8 lchip, uint16 freq);
    int32 (*peri_get_mac_led_clock)(uint8 lchip, uint16* freq);
    int32 (*peri_set_gpio_mode)(uint8 lchip, uint8 gpio_id, ctc_chip_gpio_mode_t mode);
    int32 (*peri_set_gpio_output)(uint8 lchip, uint8 gpio_id, uint8 out_para);
    int32 (*peri_get_gpio_input)(uint8 lchip, uint8 gpio_id, uint8* in_value);
    int32 (*peri_phy_link_change_isr)(uint8 lchip, uint32 intr, void* p_data);
    int32 (*peri_get_chip_sensor)(uint8 lchip, void* sensor);
    int32 (*peri_set_sensor_monitor)(uint8 lchip, void* sensor_monitor);
    int32 (*peri_get_sensor_monitor)(uint8 lchip, void* sensor_monitor);
    int32 (*peri_set_phy_sample_offset)(uint8 lchip, ctc_chip_mdio_para_t* p_mdio_para);
    int32 (*peri_get_phy_sample_offset)(uint8 lchip, ctc_chip_mdio_para_t* p_mdio_para);
    int32 (*peri_set_phy_sample_edge)(uint8 lchip, ctc_chip_mdio_para_t* p_mdio_para);
    int32 (*peri_get_phy_sample_edge)(uint8 lchip, ctc_chip_mdio_para_t* p_mdio_para);
};
typedef struct sys_usw_mchip_peri_s sys_usw_mchip_peri_t;

struct sys_usw_mchip_ptp_s
{   int32 (*ptp_init)(uint8 lchip, void* ptp_global_cfg);
    int32 (*adjust_clock_offset)(uint8 lchip, void* p_offset);
    int32 (*set_device_type)(uint8 lchip, uint8 device_type);
    int32 (*add_device_clock)(uint8 lchip, void* clock);
    int32 (*remove_device_clock)(uint8 lchip, void* clock);
    int32 (*set_ajust_delay)(uint8 lchip, uint32 gport, uint8 type, int64 value);
    int32 (*get_clock_timestamp)(uint8 lchip, void* timestamp);
	int32 (*set_input_select)(uint8 lchip, uint32 value);
	int32 (*set_sync_intf)(uint8 lchip, void* p_config);
	int32 (*get_sync_intf)(uint8 lchip, void* p_config);
	int32 (*add_session)(uint8 lchip, void* p_session_config);
	int32 (*remove_session)(uint8 lchip, void* p_session_config);
	int32 (*get_session_cfg)(uint8 lchip, void* p_session_config);
	int32 (*isr_tx_ts_capture)(uint8 lchip, uint32 intr, void* p_data);
    int32 (*set_clock_drift)(uint8 lchip, void* p_data);
    int32 (*get_clock_drift)(uint8 lchip, void* p_data);
};
typedef struct sys_usw_mchip_ptp_s sys_usw_mchip_ptp_t;

struct sys_usw_mchip_dmps_db_s
{
    int32  (*get_port_property)(uint8 lchip, sys_dmps_port_info_t* port_info, uint8 port_prop, void *p_value);
    uint16 (*get_lport_with_chan)(uint8 lchip, uint8 dir_bmp, uint16 chan_id);
    uint16 (*get_lport_with_subchan)(uint8 lchip, uint8 dir_bmp, uint8 core, uint8 pp, uint8 dp, uint8 sub_chan);
    uint16 (*get_lport_with_mac)(uint8 lchip, uint16 mac_id);
    int32  (*get_sub_chan_by_chan)(uint8 lchip, uint8 dir_bmp, uint16 chan, uint16* sub_chan, uint8* pp_id, uint8* dp_id);
};
typedef struct sys_usw_mchip_dmps_db_s sys_usw_mchip_dmps_db_t;

struct sys_usw_mchip_sync_ether_s
{
    int32  (*sync_ether_set_cfg)(uint8 lchip, uint8 sync_ether_clock_id, void* p_sync_ether_cfg);
    int32  (*sync_ether_get_cfg)(uint8 lchip, uint8 sync_ether_clock_id, void* p_sync_ether_cfg);
};
typedef struct sys_usw_mchip_sync_ether_s sys_usw_mchip_sync_ether_t;
/*dma*/
struct sys_usw_mchip_dma_s
{
    int32 (*dma_tcam_scan_reg_init)(uint8 lchip, void* p_chan_info, void* p_sys_desc_pad, void* p_sys_desc_info);
    int32 (*dma_tcam_scan_func)(uint8 lchip, uint16 chan);
    int32 (*dma_set_tcam_scan_mode)(uint8 lchip, uint8 mode, uint32 timer);
    int32 (*dma_sync_pkt_rx_stats)(uint8 lchip);
    int32 (*dma_sync_pkt_tx_stats)(uint8 lchip);
    int32 (*dma_pkt_tx)(uint8 lchip, ctc_pkt_tx_t* p_pkt_tx);
    int32 (*dma_pkt_rx)(uint8 lchip, uint8 chan_id, void* p_thread_info);
    int32 (*dma_set_pkt_timer)(uint8 lchip, uint32 timer, uint8 enable);
    int32 (*dma_set_session_pkt)(uint8 lchip, uint16 session_id, ctc_pkt_tx_t* p_pkt);
    int32 (*dma_function_pause)(uint8 lchip, uint8 chan_id, uint8 en);
    int32 (*dma_sync_hash_dump)(uint8 lchip, void* p_pa, uint16* p_entry_num, void* p_data);
    int32 (*dma_set_packet_timer_cfg)(uint8 lchip, uint16 max_session, uint16 interval, uint16 pkt_len, uint8 is_destroy);
    int32 (*dma_init_reg_buffer_scan)(uint8 lchip, void* p_tmp_chan_info);
    int32 (*dma_batch_func)(uint8 lchip, void* p_batch);
    int32 (*dma_info_func)(uint8 lchip, uint8 chan);
    int32 (*dma_stats_func)(uint8 lchip, uint8 chan);
    int32 (*dma_pkt_tx_array)(uint8 lchip, ctc_pkt_tx_t** p_tx, uint32 cnt);
    int32 (*dma_read_table)(uint8 lchip, void* tbl_cfg);
    int32 (*dma_write_table)(uint8 lchip, void* tbl_cfg);
    int32 (*dma_reset)(uint8 lchip);
};
typedef struct sys_usw_mchip_dma_s sys_usw_mchip_dma_t;

/*fdb*/
struct sys_usw_mchip_fdb_s
{
    int32 (*dsmac_decode)(uint8 lchip, void* psys, uint32 ad_index, void* p_ds_mac);
    int32 (*dsmac_encode)(uint8 lchip, void* p_ds_mac, void* psys);
    int32 (*key_encode)(uint8 lchip, void* p_ds_key, uint32* hw_mac, uint32 fid, uint32 ad_index);
};
typedef struct sys_usw_mchip_fdb_s sys_usw_mchip_fdb_t;

struct sys_usw_mchip_api_s
{
    sys_usw_mchip_lag_t * p_mchip_lag;
    sys_usw_mchip_1ae_t * p_mchip_1ae;
    sys_usw_mchip_dmps_t * p_mchip_dmps;
    sys_usw_mchip_ipuc_t * p_mchip_ipuc;
    sys_usw_mchip_acl_t * p_mchip_acl;
    sys_usw_mchip_scl_t * p_mchip_scl;
    sys_usw_mchip_l3if_t * p_mchip_l3if;
    sys_usw_mchip_ipfix_t * p_mchip_ipfix;
    sys_usw_mchip_aging_t * p_mchip_aging;
    sys_usw_mchip_nh_t * p_mchip_nh;
    sys_usw_mchip_misc_t * p_mchip_misc;
    sys_usw_mchip_paser_t * p_mchip_paser;
    sys_usw_mchip_hash_t * p_mchip_hash;
    sys_usw_mchip_qos_t * p_mchip_qos;
    sys_usw_mchip_security_t * p_mchip_security;
    sys_usw_mchip_diag_t * p_mchip_diag;
    sys_usw_mchip_mon_t * p_mchip_monitor;
    sys_usw_mchip_flowstats_t *p_flow_stats;
    sys_usw_mchip_macstats_t *p_mac_stats;
    sys_usw_mchip_npm_t * p_mchip_npm;
    sys_usw_mchip_mirror_t * p_mchip_mirror;
    sys_usw_mchip_interrupt_t *p_mchip_intr;
    sys_usw_mchip_port_t *p_mchip_port;
    sys_usw_mchip_eunit_t* p_mchip_eunit;
    sys_usw_mchip_packet_t * p_mchip_packet;
    sys_usw_mchip_xdata_t * p_mchip_xdata;
    sys_usw_mchip_oam_t * p_mchip_oam;
    sys_usw_mchip_flexe_t * p_mchip_flexe;
    sys_usw_mchip_srv6_t * p_mchip_srv6;
    sys_usw_mchip_aps_t * p_mchip_aps;
    sys_usw_mchip_peri_t * p_mchip_peri;
    sys_usw_mchip_ptp_t * p_mchip_ptp;
    sys_usw_mchip_dmps_db_t * p_mchip_dmps_db;
    sys_usw_mchip_sync_ether_t * p_mchip_sync_ether;
    sys_usw_mchip_dma_t* p_mchip_dma;
    sys_usw_mchip_fdb_t* p_mchip_fdb;
    sys_usw_mchip_serdes_t* p_mchip_serdes;
};

typedef struct sys_usw_mchip_api_s  sys_usw_mchip_api_t;

#define SYS_FEATURE_CAP   0 /*feature capbility*/
#define SYS_FEATURE_EN    1 /*feature enable*/
#define SYS_FEATURE_INIT 2 /* feature enable by init_profile */
#define SYS_FEATURE_PP_EN 3 /*feature pp enable, for at*/

struct sys_usw_mchip_s
{
    sys_usw_mchip_api_t *p_mchip_api;
    uint32 *p_capability;
    uint8 feature[CTC_FEATURE_MAX];       /**< bit0: feature capbility; bit1:feature en; bit2:feature init; bit3: feature pp en, for AT. refer to SYS_FEATURE_XXX*/
    uint8 sub_feature[SYS_SUB_FEATURE_MAX];
    sal_mutex_t*  lag_block_mutex;        /**< mutex for linagg/stacking port block */
};
typedef struct sys_usw_mchip_s sys_usw_mchip_t;


#define MCHIP_CAP(type) p_sys_mchip_master[lchip]->p_capability[type]
#define MCHIP_FEATURE_CAP(lchip,fea) (p_sys_mchip_master[lchip]->feature[fea]& (1 << SYS_FEATURE_CAP))
#define MCHIP_FEATURE_EN(lchip,fea) (p_sys_mchip_master[lchip]->feature[fea]& (1 << SYS_FEATURE_EN))
#define MCHIP_FEATURE_INIT(lchip,fea) (p_sys_mchip_master[lchip]->feature[fea]& (1 << SYS_FEATURE_INIT))
#define MCHIP_FEATURE_PP_EN(lchip,fea) ((p_sys_mchip_master[lchip]->feature[fea]& (1 << SYS_FEATURE_PP_EN)) >> SYS_FEATURE_PP_EN)
#define MCHIP_SUB_FEATURE_CAP(lchip,sub_fea) (p_sys_mchip_master[lchip]->sub_feature[sub_fea]&0x01)

#define MCHIP_1AE(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_1ae
#define MCHIP_LAG(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_lag
#define MCHIP_DMPS(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_dmps
#define MCHIP_IPUC(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_ipuc
#define MCHIP_ACL(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_acl
#define MCHIP_SCL(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_scl
#define MCHIP_L3IF(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_l3if
#define MCHIP_IPFIX(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_ipfix
#define MCHIP_LA(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_aging
#define MCHIP_NH(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_nh
#define MCHIP_MISC(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_misc
#define MCHIP_PARSER(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_paser
#define MCHIP_HASH(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_hash
#define MCHIP_QOS(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_qos
#define MCHIP_SECURITY(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_security
#define MCHIP_DIAG(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_diag
#define MCHIP_MON(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_monitor
#define MCHIP_F_STATS(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_flow_stats
#define MCHIP_MAC_STATS(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mac_stats
#define MCHIP_NPM(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_npm
#define MCHIP_MIRROR(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_mirror
#define MCHIP_INTR(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_intr
#define MCHIP_PORT(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_port
#define MCHIP_EUNIT(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_eunit
#define MCHIP_PACKET(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_packet
#define MCHIP_XDATA(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_xdata
#define MCHIP_OAM(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_oam
#define MCHIP_FLEXE(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_flexe
#define MCHIP_SRV6(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_srv6
#define MCHIP_APS(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_aps
#define MCHIP_PERI(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_peri
#define MCHIP_PTP(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_ptp
#define MCHIP_DMPS_DB(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_dmps_db
#define MCHIP_SYNC_ETHER(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_sync_ether
#define MCHIP_DMA(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_dma
#define MCHIP_FDB(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_fdb
#define MCHIP_SERDES(lchip) p_sys_mchip_master[lchip]->p_mchip_api->p_mchip_serdes


#define MCHIP_LAG_BLOCK_LOCK(lchip) \
    if (p_sys_mchip_master[lchip]->lag_block_mutex) sal_mutex_lock(p_sys_mchip_master[lchip]->lag_block_mutex)

#define MCHIP_LAG_BLOCK_UNLOCK(lchip) \
    if (p_sys_mchip_master[lchip]->lag_block_mutex) sal_mutex_unlock(p_sys_mchip_master[lchip]->lag_block_mutex)



extern sys_usw_mchip_t  *p_sys_mchip_master[CTC_MAX_LOCAL_CHIP_NUM_PP];

int32
sys_usw_mchip_init(uint8 lchip);

int32
sys_usw_mchip_set_feature_en(uint8 lchip, uint8 feature);

int32
sys_usw_mchip_set_feature_pp_en(uint8 lchip, uint8 feature);

int32
sys_usw_mchip_deinit(uint8 lchip);

#ifdef __cplusplus
}
#endif

#endif

